- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello!
In the Double Data Rate I/O Megafunctions datasheet it is said, that DDR output data port of ALTDDIO_OUT ( dataout[] ) should directly feed output pins in top-level design. But in my design I need to feed these outputs to inputs of another block inside my design. That , of course, causes Quartus errors. Is there a workaround for this problem?Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hello! In the Double Data Rate I/O Megafunctions datasheet it is said, that DDR output data port of ALTDDIO_OUT ( dataout[] ) should directly feed output pins in top-level design. But in my design I need to feed these outputs to inputs of another block inside my design. That , of course, causes Quartus errors. Is there a workaround for this problem? --- Quote End --- DDR is meant for external interfacing only. Inside fpga there is no ddr support as you can just double your clock.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
And you can just build it in RTL. The altddio_out is meant to call the dedicated structure built in the I/O cell.

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page