ALTGX PIPE byte order alternates for each SKP ordered set received

[Altera_Forum]

I’m working on a PCI Express Protocol Analyzer design which uses an Arria II GX (EP2AGX45DF29C5). An external probe creates copies of the x4 Host-to-Device (H2D) and x4 Device-to-Host (D2H) data which is then sent into the AIIGX via two ALTGX instances, each in bonded x4 configuration. My FPGA Fabric logic retrieves the data via the PIPE interface, byte orders it, descrambles it etc.  

 As the title states; I’m seeing a PCIe card that sends back-to-back SKP Ordered Sets interleaved with SDP Packets. See attached Protocol Analyzer trace (‘1 - SKP_SKP_SDP_SKP_SKP.jpg’). The cursors show that there is 4.720 us between each SKP ordered set. Also attached are the corresponding views from my STPII Trace (‘2 - crossed_SKP_ordered_set.jpg’ and ‘3 - not_crossed_SKP_ordered_set.jpg’). Both these STP traces show key locations within the attached .STP trace (‘H2D_D2H_alternating_byte_order.stp’). The signals in the trace that comes directly from the ALTGX instances are D2H_GX_K/ D2H_GX_D and H2D_GX_K/ H2D_GX_D.  Since the byte ordering coming out of the 16-bit PIPE data is random depending on when the PCS comes out of reset, I have a “byte ordering module” that detect whether the COM character is received in the lower or upper byte during reception of the SKP ordered sets (COM/SKP/SKP/SKP == BC/1C/1C/1C). If COM is received in the upper byte then the byte order will be reversed. As can be seen from the H2D signal in the STP trace, this works correctly on the H2D link because the byte ordering coming out of the H2D ALTGX instance is consistent. However, the byte order of the data coming out of the D2H ALTGX instance alternates between ‘not crossed’ and ‘crossed’ (where ‘crossed’ means that the COM is located in the upper byte of the 16-bit PIPE data. This behavior makes it impossible to correctly byte order the lane data because a correctly ordered SDP Packet sometimes arrives right after an incorrectly (crossed) ordered SKP Ordered set!  It appears the byte ordering module within the PCS for some reason is enabled on the D2H ALTGX instance and that the byte ordering is toggled for each and every SKP Ordered Set received. The byte ordering block built into the FPGA should not be active in PIPE mode but somehow the incoming data causes trouble for the ALTGX instance?  Note that the H2D link direction has a consistent byte ordering after reset.   I'm using QII Web Ed. v 13.0 (screenshots were made with v 11.1 which behaves the same).  Thanks,  /John.