hello
In my project, based on Stratix IV GX (EP4SGX530HF40C2), I have design that controls fast quad serial ANALOG Devices A/D AD9639.
From the FPGA, there are diffrential LVDS Encode (clk) of 100Mhz signals to the A/D for sampling the analog input signal.
The diffrential clkdesign is based on ALTGX_PLL. The phase noise of the Reference osc to ALTGX_PLL has phase noise of 160 dbc/hz.
The questions are:
1. what is the typical skew value of the diffrential clk that gets out of ALTGX_PLL ?
2. What is the phase noise or the jetter ?
thanks.
ori
