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I'm receiving data via the ALTGX PIPE interface (PCI Express). I'm seeing that the byte ordering is random. The Arria II GX handbook states (page 1-35) that
"Byte Ordering Depending on when the receiver PCS logic comes out of reset, byte ordering at the output of the byte deserializer may not match the original byte ordering of the transmitted data. The byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset." and "The byte ordering block looks for the user-programmed byte ordering pattern in the byte-deserialized data. You must select a byte ordering pattern that you know appears at the LSByte(s) position of the parallel transmitter data. If the byte ordering block finds the programmed byte ordering pattern in the MSbyte(s) position of the byte-deserialized data, it inserts the appropriate number of user-programmed PAD bytes to push the byte ordering pattern to the LSByte(s) position, thereby restoring proper byte ordering." Apparently, the byte ordering block is not part of the PCS in PIPE mode. Then, how can I find the order of the bytes as they were sent on the wire? I suppose I could detect the COM+SKP+SKP+SKP ordered set which is periodically sent and swap the bytes if in the incorrect order. This, however, will not work when receiving the PCI Express compliance test pattern or some other data that may not have the SKIP ordered set in it (for some reason).Link Copied
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After having done additional research on this topic, I have found that I should swap the bytes when I receive a COM symbol on the lower byte of the 16-bit data. The compliance pattern is 4 symbols long and is sent with the COM symbol first so should be received with the COM symbol in the LSByte on the pipe interface. When receiving one of the ordered sets, the same applies.
I have verified and this works for the compliance pattern. I have yet to validate the functionality with actual ordered sets but should work too.
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