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Hi,
I'm trying to use AN638 Reference Design to run on two boards (one to transmit, one to receive). I modified the packet generator to generate my own packets, and the packet monitor to recognize them. I was able to confirm that it was able to send and receive on ModelSim. Using real Stratix IV 530 Development Boards, however, I'm unable to get the same results. Using SignalTap, I can see the packet is sent from one board and received on the other board by tapping xgmii_tx_data and xgmii_rx_data, respectively. However, following the data through the Eth 10G Mac, the data disappears at the rx_eth_lane_decoder module. Tapping that module specifically, I can see the input data and the clock running fine, but no intermediate or output signals are changing at all. Can anyone who's used this design or is familiar with the Eth 10G Mac core shed some light on what I might've done wrong? Thanks.Link Copied
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After doing some more testing, it seems to be a problem with the XAUI-SFP+ board. I was able to use the HSMC loopback card and the 10G Mac was able to read those packets. However, after reconfiguring the project so that the data transmits from channel 2 of the board and receives from channel 1. This, however, causes the same issue as the two-board configuration.
Does anyone know how to go about debugging signals going through the HSMC board?
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