Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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AS Flash pins access

Altera_Forum
Honored Contributor II
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Hi All, 

 

I'm trying to access the top portion of the Configuration flash using my own logic. I've been using a separate flash (same chip) and have the driver written but want to save the space and use what already there. Unfortunately, Quartus gives a "dual" assignment warning even after I set up the pins to use as user I/O after configuration. 

Looks like this. 

 

Error: Can't place multiple pins assigned to pin location Pin_C1 (IOPAD_X0_Y25_N7) 

Info: Pin FLASH_DI is assigned to pin location Pin_C1 (IOPAD_X0_Y25_N7) 

Info: Pin ~ALTERA_ASDO_DATA1~ is assigned to pin location Pin_C1 (IOPAD_X0_Y25_N7) 

 

Are these pins only useable via "mega functions" or are they truely released to user I/O after config? 

 

Thanks, 

Steve
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Altera_Forum
Honored Contributor II
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Skip this question. I figured it out by trial and error. No thanks to Altera Documentation. I guess they expect everyone to blindly follow the NIOS/megafunction path without actually knowing how the hardware works. Keeps us locked into their product that way. 

 

For those of you interested and who actually write your own hardware drivers rather than using the cookbook megafunctions: 

 

The "Enable input tri-state on active configuration pins in user mode" check box will conflict with user mode access on the configuration pins.
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