Hi,
In our current product line, we use Cyclone and Arria FPGAs which are configured via Passive Serial mode directly from the host CPU. The implementation uses a simple SPI interface and a few GPIOs. This approach has proven to be both fast and reliable, with minimal hardware requirements.
Due to an end-of-life situation with our current CPU, we are planning to update our platform. As part of this redesign, we are also considering replacing the Cyclone/Arria FPGAs with Agilex devices to stay current.
However, we've discovered that Passive Serial mode is no longer supported on Agilex devices. We're now looking for an alternative method to configure the FPGA directly from the CPU, ideally without requiring additional components.
As far as we understand, the only comparable "passive" configuration mode on Agilex is via the Avalon-ST (AVST) interface. Unfortunately, our new CPU platform does not have dedicated hardware support (like SPI) for this. The only feasible way to drive AVST would be by bitbanging the signals in software.
We are confident we can meet the minimum timing requirements of the AVST interface, but we cannot guarantee a perfectly constant AVST_CLK frequency due to CPU load and scheduling.
Will an AVST_CLK signal with minor frequency variation (caused by bitbanging) cause issues during configuration? Or does the configuration logic in the FPGA/SDM strictly require a stable, free-running clock?
Best Regards
