AXI or Avalon MM

[Altera_Forum]

Hello there, 

 So i'm busy with deciding on which interface I will implement in the FPGA fabric of my design.  In the documention they say you can choice either for AXI or Avalon-MM. I tend to go for the AXI bus because this way i don't have to translate the Avalon-MM to AXI interface and the complition signal is also usefull.  But then i'm thinking, why would you use Alvalon-MM ?   And connected to this question. I want to connect my own FPGA blocks with Port map ( A => B ), Not using Qsys, (because Qsys automatically uses Avalon) to the AXI interface. would this be even possible ?   I was hoping some of you have more experiance with these interfaces and willing to help me out.   Cheers, Hidde

[Altera_Forum]

Both buses are need ! 

All Altera-s IP-cores maked with Avalon historical, and AXI is base in ARM processor and linking all peripheral to it. May be adapters AXI-Avalon and back, even in examples, search !

[Altera_Forum]

--- Quote Start ---   In the documention they say you can choice either for AXI or Avalon-MM. I tend to go for the AXI bus because this way i don't have to translate the Avalon-MM to AXI interface and the complition signal is also usefull.    --- Quote End ---   Qsys will insert adapter logic, so the need for conversion is less of a concern.  Personally I would base the decision on which interface is well-supported by Altera's verification suite. Up until recently, only the Avalon-MM interfaces had decent verification support, i.e., BFMs. Altera does have support for AXI, but its via Mentor Graphics BFMs. I have not tested the AXI BFMs.    --- Quote Start ---   And connected to this question. I want to connect my own FPGA blocks with Port map ( A => B ), Not using Qsys, (because Qsys automatically uses Avalon) to the AXI interface. would this be even possible ?   --- Quote End ---   Yes, its trivial. I have a number of designs with a single Avalon-MM master (based on an FTDI USB-to-FIFO bridge) and one or a few slaves (RAM + registers) and for testing I just connect those directly together.  However, its also easy to connect them with Qsys. The generated code is easy to read, so you can open up the top-level file and check that the Qsys system matches what you expect.  Cheers, Dave

[Altera_Forum]

Thnx, really helpful comment.  

 Is there any reason why one should want to use AXI within FPGA fabric, apart from your IP is AXI or your customer wants it ? Because i'm trying to figure out the pro's and con's of having AXI or Avalon.  thanks in advanced.  Cheers, Hidde

[Altera_Forum]

Hi Hidde, 

  --- Quote Start ---   Is there any reason why one should want to use AXI within FPGA fabric, apart from your IP is AXI or your customer wants it ? Because i'm trying to figure out the pro's and con's of having AXI or Avalon.   --- Quote End ---   It comes down to what you want to use the code you develop for. If I was writing code to target Altera and Xilinx devices, then I would create AXI components. If the code is specific to an Altera design, and I care more about ease of verification, then I'd write Avalon components.  You should apply the same philosophy as coding-style, i.e., use a style that matches the project code-base. In your case, if your Qsys system contains a lot of Avalon-MM components, then write the new components with Avalon-MM interfaces too. It will make the long-term maintenance of the code (potentially) easier (due to the common bus standard used in the code).  Cheers, Dave

[Altera_Forum]

thank you for the Hints&Tips. That was really useful. We have decided to use avalon as standard bus. It better suites our needs.

[Altera_Forum]

--- Quote Start ---  We have decided to use avalon as standard bus.  --- Quote End ---   Great!  For examples of the Avalon-MM Verification IP, see these threads;  http://www.alteraforum.com/forum/sho...t=32952&page=3 http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial http://www.alteraforum.com/forum/showthread.php?t=34787  Cheers, Dave