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About pin states from the end of MAX10 configuration to transition to user mode

Yamada1
Beginner
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According to the Intel® MAX® 10 FPGA Configuration User Guide, logic and registers are initialized and I/O buffers are enabled after configuration is complete. It would be helpful if you could teach me the following points.

1) Does this mean that the register is initialized to '0'?

2) Is it correct that logic initialization means finalizing the logic of the design? Also, if the logic input is connected to an I/O buffer, is it set to '0' or '1' at initialization?

3) If the understanding in 1) is incorrect, is it correct to understand that the register will have the initial value according to the design? (If it becomes '1' with a synchronous or asynchronous reset, that register becomes '1' with initialization, etc.)

 

We apologize for the inconvenience and appreciate your understanding.

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NurAiman_M_Intel
Employee
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Hi,


  1.  Logic are initialized to 0, but IO buffer status during configuration stage is = TRISTATE/HIGH-IMPEDANCE(HIGH-Z)
  2. If logic IO port connected to input/output IO-> during configuration state, all IO buffers are set to TRISTATE/HIGH-IMPEDANCE/HIGH-Z regardless of the logic status. 
  3. YES


Regards,

Aiman


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Yamada1
Beginner
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Thank you for your reply.

 

I'm sorry to ask a second question, but I would appreciate it if you could explain the following points.

1) You said that the logic is initialized to '0', but does this mean that the final output will be '0' regardless of the configuration? If the logic Y=(A and B) or (C and D) is configured and this is initialized, does that mean that Y='0' will be the result if it is initialized regardless of the values ​​of A to D?

2) You said that all I/O buffers are TRISTATE/HIGH-IMPEDANCE/HIGH-Z, but if the logic Y=(A and B) or (C and D) is initialized, what values ​​will A to D have?

 

I apologize for the trouble, but thank you in advance.

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FvM
Valued Contributor III
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Hi,
when starting user mode, registers are initialized to 0 unless explicitly defined otherwise in your logic description.
Unregistered (combinational) signals are getting a logic level according to defined logic, this applies of course to unregistered outputs as well.
I don't understand your initial point 2. Inputs are getting the state driven to it externally. In case you are asking about non- tristated INOUT pins, they are reading back the state driving to it from the FPGA.
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Yamada1
Beginner
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Thank you for your answer.
 
I apologize for not being clear enough.
NurAiman_M_Intel told me that the I/O buffer during initialization will be TRISTATE/HIGH-IMPEDANCE/HIGH-Z regardless of the logic state.
So, if the logic is Y=(A and B) or (C and D) and Y, A, B, C, and D are connected to INOUT pins, then I wanted to know what state A, B, C, and D will be at the time of initialization (0, 1, Hi-Z, the external state of the input pin is visible as is, etc.), which is the intention of question 2).
 
I apologize for the trouble, but thank you in advance.
 
 
 
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NurAiman_M_Intel
Employee
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Hi,


After configuration complete, if you define the initial state of the design '0', A B C or D will be '0'. If you define it as '1' then the state is '1'. But for your information, before that happened, all of this are in tri state, hence it cannot be modified.


Regards,

Aiman


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NurAiman_M_Intel
Employee
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Hi,


Any other information needed for this case? Else I will proceed to close this case for now.


Regards,

Aiman


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NurAiman_M_Intel
Employee
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We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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