About the cycloneIII IO output speed

[Altera_Forum]

hi everybody 

I'm trying to use the EP3C25F324C8 to generate 250MHz clock as high speed AD（AD9481） clock，could it work？I don't know if the user IO (3V3 LVTTL)or PLL output pins can support this output speed.    PS: Sorry my english is not good enough@_@

[Altera_Forum]

setup an empty quartus project with your target fpga selected, you can use the web edition 

 then start the megacore wizzard and try to setup a pll with your input clock and output clock, then you will see what frequency this device will be able to generate. but what fmax you will reach with your design is a different thing.

[Altera_Forum]

Assuming that you successfully manage to generate a 250MHZ clock in your FPGA then 250MHz is probably too fast for LVTTL outputs. 

 Consider using differential LVDS or similar standards for output pins

[Altera_Forum]

--- Quote Start ---  I don't know if the user IO (3V3 LVTTL)or PLL output pins can support this output speed.  --- Quote End ---  You could know if simply consulting the Cyclone III Hardware Handbook. 250 MHz isn't supported with C8 speed grade and 3.3 or 3V single ended I/O's. I suggest, to wire the clock differentially.

[Altera_Forum]

thank you everyone，I think I should try another way. LVDS maybe the bast way unless use external PLL. Can I use the LVDS out as the high speed ADC  

clock? I am worry about the jitter in the clock.

[Altera_Forum]

Jitter can be generally expected to be lower with differential I/O standard. The ADC clock input can be possibly also driven from a single ended output not exactly complying LVTTL or LVCMOS IO specifications, you should should check the datasheet details. But a differential connection is surely less susceptible to common mode noise, which is most likely the dominant jitter source. Unfortunately, also the FPGA input clock jitter is critical in this respect, so you may want to use a differential interface for minimum jitter in this place, too.

[Altera_Forum]

The AD9481 I using is driven by differential clock input, but datasheet is not point out the standard. The VCOM of the clock is about 1.25V, and 400mV Vp-p, maybe can driven by LVDS directly.

[Altera_Forum]

The AD9481 datasheet suggests AC coupling of the clock input and specifies a minimum level of 200 mVpp. Thus all differential IO standards available with C III should be suitable, I think.