Hi all!,
I have pin connection in top module that:
.PixBus ( { PixParaBus[11:1], dummy } ),
and PixParaBus is output pin.
this is declaration about PixParaBus:
output [11:0]PixParaBus
Now, PixBus changes rapidly.
So, the change is reflected on PixParaBus, which is real output pin,
and dummy is works as dummy.
It does not influence any pin, wire and/or reg.
And, PixParaBus[0] is assigned to GND.
This is OK.
But, I run into such strange problem.
If I rewrite PixBus connection that:
.PixParaBus ( PixParaBus[11:0] ),
and delete about PixParaBus[0] connection and dummy, I got problem.
The synthesis has gone well, but the PixParaBus changes very slowly,
and I think PixBus which is from below module changes slowly too.
Why the difference of what wire is connected to below module has very influence to below module and below module works as so differently??
I have no idea.
plz Help!
thx!
