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I am trying to interface fpga and yocto in DE2i-150 board using device driver. From software side I am using DMA for memory allocation. I have 3 input data. Two of them are 416 bit long and one is 32 bit long. I am writing 416 bit long data first to memory using pci_dma_read .I want to read this data in my verilog file which is running in hardware side. How can I access this specific memory for this data in verilog file where I have a read input of 32 bits?
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--- Quote Start --- How can I access this specific memory for this data in verilog file where I have a read input of 32 bits? --- Quote End --- Your question is not clear. If you are implementing a 32-bit bus master, then you just need to read your (416 bit) data using several 32-bit transactions. Maybe post your existing project and/or a diagram of what you are trying to do? You may want to consider not storing your data in memory, and instead just DMA it into registers in your component (sometimes, implementing a slave is more straightforward than implementing a master).
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I am trying to implement an application where in software side I have A(416 bits), B(416 bits), C(416 bits), D(32bits), E(32bits) which I have to pass to the fpga for computing some arithmetic operations. My output is of 96bits. I am new to this field, so I don't have much knowledge regarding this. What I have done is, I have followed "Using PCI express on DE4 boards" and implemented the driver as described there. I am sending the data using the function "alt_up_pci_read" and "alt_up_pci_dma_add". In my verilog files I have used a array of 32bit registers to store the 416 bit data coming from the software side. But I am not sure how this will work if I just DMA the values to the registers. Do I need to have some offset or anything like memory access or do some extra thing in that case? Or only input will suffice?
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Until you get the hang of things, leave DMA out of it. Just use alt_up_pci_write() to send your inputs, and alt_up_pci_read() to retrieve your module outputs. Then after you get it working, build up to using the DMA.
Yes, you need to know your offsets within your module. It will depend on how you implemented your address decoding within your module that you wrote.- Mark as New
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Thank you for your response. I have resolved that problem. Now I am facing another problem related to onchip memory range. I don't want to use Nios II. I just want to speed up the arithmetic computation I mentioned before using parallel ckt. I have implemented a custom logic for this which I have declared as avalon master. I am accessing memory upto 176byte and No of address bits required is 8. But whenever I am trying to connect custom logic avalon master to onchip memory s2, I am getting the following error: Error: System.gmm_0.avalon_master: shared_memory.s2 (0x0..0x1fff) is outside the master's address range (0x0..0xff). Memory size I have given as 8192byte. How to resolve this issue?
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You need to increase the address width of the Avalon Master to meet or exceed the width of the address space you have connected I to.
The error is telling you that as-is your master cannot possibly address some slaves that you have connected it to, and it wont let you do that.
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