Accessing user data in configuration flash

[pgigliotti]

I have two designs (Arria V and Cyclone V) both using EPCQ256 flash memories for configuration of the FPGAs.  After configuration, I need to use a home grown SPI controller to access this memory (both read and write accesses).  I am specifically interested in what I need to do to take over these configuration pins.

[FvM]

Hi,
all you need to do is to declare all involves AS pins as IO in user mode. I'm mostly using altasm_parallel to access flash memory.

[pgigliotti]

It sounds easy enough, but is there anything I need to do to assign in user mode, besides just using them in the design and constraining them to the AS pins?

[FvM]

Instantiate the flash controller of your choice and try to compile.

[pgigliotti]

When we try to assign the pins in the Pin Planner, it gives an error message that the pins are “not assignable”.  When we do it manually in the Assignment Editor window and in the QSF file, but when we try to compile after that, it fails on the Fitter saying it “cannot place the components due to conflicts with existing constraints”.

We searched the issue online, and there was an Intel support page saying the pins not being assignable in user mode is an issue with Quartus, and to add two lines to the QSF file. we added those lines, but it gave usthe same issue when trying to compile. (Here’s the link to that page: How do I assign dual-purpose pins to be a user I/O after... (intel.com))

If there’s anything else you think we should try, let us know. 

[Fakhrul]

Hi pgigliotti,

Can you execute the suggestions provided by our community member earlier?

Regards,

Fakhrul

[Fakhrul]

Hi pgigliotti,

I wish to follow up with you about this case. Do you have any further questions on this matter? Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.

Regards,

Fakhrul

[Fakhrul]

Hi pgigliotti,

I wish to follow up with you about this case. Do you have any further questions on this matter? Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.

Regards,

Fakhrul

[pgigliotti]

I hope to have an answer later today, as to the viability of this solution.

[pgigliotti]

When we try to assign the pins in the Pin Planner, it gives an error message that the pins are “not assignable”.  When we do it manually in the Assignment Editor window and in the QSF file, but when we try to compile after that, it fails on the Fitter saying it “cannot place the components due to conflicts with existing constraints”.

We searched the issue online, and there was an Intel support page saying the pins not being assignable in user mode is an issue with Quartus, and to add two lines to the QSF file. we added those lines, but it gave usthe same issue when trying to compile. (Here’s the link to that page: How do I assign dual-purpose pins to be a user I/O after... (intel.com))

If there’s anything else you think we should try, let us know. 

[pgigliotti]

When we try to assign the pins in the Pin Planner, it gives an error message that the pins are “not assignable”.  When we do it manually in the Assignment Editor window and in the QSF file, but when we try to compile after that, it fails on the Fitter saying it “cannot place the components due to conflicts with existing constraints”.

We searched the issue online, and there was an Intel support page saying the pins not being assignable in user mode is an issue with Quartus, and to add two lines to the QSF file. we added those lines, but it gave usthe same issue when trying to compile. (Here’s the link to that page: How do I assign dual-purpose pins to be a user I/O after... (intel.com))

If there’s anything else you think we should try, let us know. 

[FvM]

You are linking a support page that is more than 10 years old referring to outdated Quartus versions.

Unfortunately we don't know your exact configuration and can't reproduce the issue. Can you archive a minimal design that demonstrates the problem?

[Fakhrul]

Hi pgigliotti,

There is a forum post related to your issue.

You may take a look and see if this is applicable.

Cyclone V spi memory access

Regards,

Fakhrul

[Fakhrul]

Since we haven't heard back from you about our previous message, we'll now move this discussion to community support. Feel free to start a new thread for any new questions or issues you have – our Intel experts will be there to help. But if you don't have more questions, the community users can still assist you here. Thanks for your understanding.

[pgigliotti · Accepted solution]

Here is the solution - Instantiate the "Intel® FPGA Serial Flash Loader IP Core" and hook up a QSPI controller to this core.

Here is a link to YOUR document - 1.9. Intel® FPGA Serial Flash Loader IP Core Signals