Across clock domains problem

Altera_Forum · ‎08-13-2013

There are two main clocks in my project, one is 250MHz, antoher is 100Mhz. A counter counting according 250MHz clock. I want to register the counter's value at some conditions, and send this value into 100MHz clock domain. The code is as bleow:


process(ck4x,reset)
begin
    if reset='0' then
       CT_cnt <= (others => '0');CT_cnt_q <= (others => '0');CT_Latch <= (others => '0');
    elsif ck4x'event and ck4x='1' then
       CT_cnt_q <= CT_cnt;CT_cnt_2q <= CT_cnt_q;hitok_q <= hitok;hitok_2q <= hitok_q;
       if LaunchCT='1' then
          CT_cnt <= CT_cnt + 1;--------The counter counting in 250MHz clock domain
       else CT_cnt <= (others => '0');
       end if;
       
       if hitok_q/=hitok_2q and hitok_q='1' then--Register CT_cnt value at the rising edge of hitok_q.
          CT_Latch <= CT_cnt_2q;
       end if;
    end if;
end process;
process(sysclk,reset)--Send the registered counter value to 100MHz domain.
begin
    if reset='0' then
       CoarseTime <= (others => '0');
    elsif sysclk'event and sysclk='1' then
       if SQOK='1' then
          CoarseTime <= CT_Latch;
       else
       end if;
    end if;
end process;

Is this across clock domains safely or not?!

PS:

1. The SQOK is generated from HITOK, HITOK is a pulse whose width is about 100ns. SQOK is generated as attached BDF design.

2. The attached another image shows HITOK, SQOK and two clocks timing relationship.

Altera_Forum · ‎08-13-2013

you would want at least a double register to get it "safely" across the domain. But how often are you going to read it? if its rather infrequently, and its set infrequently, then this method should be safe enough.

Altera_Forum · ‎08-13-2013

--- Quote Start ---

you would want at least a double register to get it "safely" across the domain. But how often are you going to read it? if its rather infrequently, and its set infrequently, then this method should be safe enough.

--- Quote End ---

Hi Tricky,

I read it after it is register correctly in 250MHz clock domain, so i generate SQOK signal to ensure that. It means the counter is read in 100MHz clock domain very later than it is registered in 250MHz clock domain, i can control the the SQOK postion(reading time point) as the BDF shows. I think it really like data exchange across clock domains using handshake control signals, am i right?

Thanks

Jerry