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Active serial configuration

MCipr5
Novice
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Hi everyone,

 

I'm trying to repair a board because can't load the configuration from external device,

details below...

 

For my design I'm using 5SGXMA3E2H29I2L and EPCQ256SI16N.

I checked every connection, power and MSEL pins and everything is correct.

 

I noticed that the signals nCS and DCLK are behaving differently from a working board.

 

DCLK on the good board runs to capture data from the flash and the nCS is obviously low.

On the faulty board, nCS is pretty much always high (see attached image) and DCLK signal is always high.

 

It seems like the FPGA is booting differently.

 

Can someone help me?

 

Thanks

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lixy
Employee
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Hi,


Can you please also test the waveform of nCONFIG, nSTATUS, CONFIG_DONE, INIT_DONE signals.


Thanks,

Xiaoyan


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MCipr5
Novice
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Hi Xiaoyan,

 

Here:

 

Good Board:
nCONFIG --> HIGH
nSTATUS --> nSTATUS OK.png
CONFIG_DONE --> LOW
INIT_DONE --> HIGH

 

 

Faulty Board:
nCONFIG --> HIGH
nSTATUS --> nSTATUS KO.png

CONFIG_DONE --> LOW
INIT_DONE --> HIGH

 

 

nSTATUS KO.png below

nSTATUS KO.png

 

nSTATUS OK.png below

nSTATUS OK.png



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lixy
Employee
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Hi,


1-- nCS settings

By comparing the waveform of nSTATUS and nCS of the fault board, it seems the configuration failure is caused by the nCS signal being abnormally pulled high.

When nCS cannot be pulled low, AS configuration cannot be started, so that DCLK and nSTATUS signals are not correct.

Please check if there's difference in the nCSO pin between "Good" and "Faulty" boards, including the board connections, settings in Quartus.

2-- Good board's CONFIG_DONE is low, which indicates the Configuration is not done. How do you confirm that those ones are successfully configured? Are you just keep making the FPGA restart configuration?

3-- Can you capture the waveform with all these signals showing in the same screen? From the POR to the time failure happens.


Thanks & Regards,

Xiaoyan


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MCipr5
Novice
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Hi,

 

1-- I checked nCSO and nothing changes between the boards.

2-- I left the flash blank to have same conditions on  both boards,

      so on the good one the fpga was continuosly trying to upload the configuration.

3-- I captured the signals using nSTATUS as the trigger, here they are some images.

 

 

 

 

I tried to configure the fpga with .sof because it seems like something works,

even if nSTATUS remais low as you ca see in attached images below.

 

nSTATUS = yellow

nCONFIG= blue

CONFIG_DONE = purple

INIT_DONE = green

 

Thank you very much Xiaoyan!

 

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lixy
Employee
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Hi,

1-- Can you also test the voltage of nCSO with blank FLASH?

2-- Please check if the nSTATUS pin of good and faulty board has same connection/settings.

It seems that the nSTATUS signal of "Good" and "Faulty" Boards starts with different voltage level. As you know, the nSTATUS and nCONFIG need be connected to pull-up resisteor, which means they should start with High.

3-- Are all boards successfully configured with SOF through JTAG?

As for your question about nSTATUS, only CONFIGE_DONE signal reflects the success of JTAG configuration. Therefore, you do not need to test nSTATUS and nCONFIG signals during the JTAG config, and the trigger signal for oscilloscope should be CONF_DONE.

4-- If the faulty board is successful in JTAG Config, and the board connection/software settings are the same as the good ones, we may suspect the nCSO pin defect.


Regards,

Xiaoyan


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MCipr5
Novice
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Hi,

 

here it is the nCSO pin:

 

MCipr5_0-1678699375622.png

 

I confirm that good and faulty board has same connection/settings.

It seems like the boards succesfully get the configuration with .sof, the only difference in the faulty one, as you can see between "Good board after configuration with sof" and "Faulty board after configuration with sof", is that nSTATUS pin remains low even if I can clearly see my design running (the FPGA correctly manage two SDI video stream and multiple other signals).

Even quartus says "Succesfully ended operations"

 

 

Thanks

 

 

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lixy
Employee
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Hi, 

 

Sorry for the late response.

As I mentioned before, in the Stratix 5 user guide, there's no specific JTAG configuration waveform, but only the "CONF_DONE" signal pulling high indicating the completion of the JTAG configuration. But it is true that the nSTATUS signal of the "Faulty Board" looks not normal. So still let's make sure if FPGA is still ok to run.

  1. If sof is not configured into the "Faulty board" FPGA, it means that the function of the problem is on FPGA function. This kind of abnormal could be caused by Power. If Power is also ok, then it means FPGA itself is abnormal. 
  2. If sof is successfully configured into the FPGA, it means FPGA itself is normal. In this case, the problem is either on Board-level connection or FLASH device itself. You may try if the FLASH can work normally to read/write data. 


Thanks & Regards,

Xiaoyan


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MCipr5
Novice
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Hi Xiaoyan,

 

I decided to replace the IC, I'll let you know if it was the device.

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