How to read data from the DDR4 memory of a *Modified* PCIe DMA transfer example design.

[Sijith]

Hi,

I have a modified version of PCIe DMA transfer example design mentioned in the Chapter 7 of attached user manual (I added a custom generated data generator IP and an Avalon FIFO Memory Intel IP to the existing DMA transfer example design {Platform designer screenshot is attached as DMA_modified_part1.PNG and DMA_modified_part2.PNG}) .

My aim is to continuously generate data (bit stream) in the FPGA using a custom built data generator IP and pass it through a FIFO to the DDR4 memory, and then do a DMA transfer though the PCIe to the host computer.  Basically a continuous DMA read (just read) from the data saved in the FPGA DDR4 memory.

I would like to know what are the essential functionalities/files needed in host computer to do a continuous reading of data from the DDR4 memory.  How I can tailor the existing API's of PCIe DMA transfer example design (in which data generates in the host computer, and then write that data {though PCIe} to the DDR4 memory in the FPGA and then read it back) for my project?.

It would be great if you could point to the essential files/procedures in the DE5a-NET-DDR4 system CD/Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4 (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=228&No=1108&PartNo=4#contents) for reading data from the FPGA DDR4 memory to the host computer. Specifically, I would like to know if I have the .qpf and .qsys files (of the modified PCIe DMA transfer example design) in a directory i.e. Desktop/DDR4/, how I should set up the functionalities to read data from the DDR4. Unfortunately, I could not find any detailed information regarding this anywhere. Looking forward for a helping hand.

As we have functionalities to do DMA transfer in the example design, I am working in Arria 10 GX device (10AX115N2F45E1SG) and my host computer is based on windows 10. And I am using Quartus Prime Pro 18.4 version.

[AdzimZM_Intel]

Hello,

You refer to the following PCIe example design with external memory: https://www.intel.com/content/www/us/en/design-example/714462/arria-10-an708-pcie-gen3x8-avmm-dma-with-external-memory.html

Please let me know if that help.

Regards,

Adzim

[AdzimZM_Intel]

Hi,

I can suggest you to contact with Terasic for the details of the files that you are required.
Currently we don't have much information on that.

Regards,

Adzim