Adding non-addressable memory causes Downloading ELF Process Failed message

Altera_Forum · ‎03-22-2017

I systematically removed components and narrowed my problem to just one: a 64kB 64-bit On-chip ram that is NOT accessed/connected to the Nios II. I developed a subsytem that exclusively uses that memory. I used both Quartus Prime 16.0.0 and 16.1.2 and the corresponding Eclipse for Nios II suite.

The error is below in the console:

Downloading 00020000 (0%)

Downloading 00026E34 (82%)

Downloading 28KB in 0.4s (70.0KB/s)

Verifying 00020000 (0%)

Verify failed between address 0x20000 and 0x25B1B

Leaving target processor failed.

My 32-bit on-chip RAM is located at 0x0020000-0x0003FC97 (130KKB, connected to the Nios II. The 64-bit is 0x0-0xFFFF (64KB, not connected to Nios II but connected to custom logic. For some reason, simple presence of the 64-bit one is causing conflict, even though I'm assuming the Nios II can't address it. I tried regenerating the BSP after freshly synthesizing my design. I tried Quartus Prime 16.0 and 16.1.2. BSP editor screenshots are attached. Again, the 64-bit memory is not connected at all to the Nios II, but this problem goes away when I disconnect it from my sub-circuit. I've look through all related forum entries...to no avail.

Anyone have any ideas why this might be happening? I can upload any other screenshots. (I hope the ones attached can be read).

Altera_Forum · ‎03-23-2017

I'm presuming the 64kb memory is removed from the design in your last screenshot. When it is included in the system, how is it connected? You mention that it's in a subsystem. How is that subsystem connected to the rest of the design?

Altera_Forum · ‎03-23-2017

sstrell,

I attached the sub-module screenshot to this reply. The memory is connected as a slave to two other modules (hcam_outb and hcam_inb).

In the topleve the submodule is connected with two pairs of Avalon-ST sinks/sources, some Avalon-MM interfaces for statistics, and two exported LEDs. The 64KB memory module is not exported at all.

Altera_Forum · ‎03-28-2017

Well, seems I found my problem. I was definitely failing timing. I'm still working out timing in the whole design, but the 64KB of on-chip memory added many cycles worth of slack for some reason; all default tests failed. I reduced to 5KB, and I am now off time by 5ns. The design at least loads, but I need to add a few pipelines in my design.

For anyone else who has this problem, ensure you meet timing!!