Advantages of LPM_COMPARE vs. LPM_XOR vs. XOR when comparing two 32 bit numbers

[Altera_Forum]

Hi, 

 I need to compare two numbers in a combinational circuit. The inputs are two 32 bit numbers. The output is a single bit and should be "1" when both inputs are equal and 0 when they are not. I am using Verilog in my project  There are many ways in which this can be accomplished but at this time I think I can do this in the following forms:  

1. Using LPM_COMPARE (using the a=b output port), 
2. Using LPM_XOR (size 2 width 32) with its 32 bit output connected to 32 input NOR 
3. or with 32 XOR primitives followed by a 32 input NOR 

  I need to know from the point of view of synthesis of the circuit, which of the above methods is the most efficient one. I do not really care much about compilation time as my main constrain is the space I have in my device. I am trying to optimize it as much as possible.  Note: I understand that optimizing the area for this circuit may not do much for my overall project footprint, but my main objective now is to get a better idea on how synthesis works so that I can make better decisions on what components to use and how to organize them to get the most area efficient design  The manual for the LPM_COMPARE indicates that it uses an adaptive lookup table , how does this compare, in terms of resource usage, against organizing the circuit with pure XOR and NOR primitives? Any comments on this topic will be appreciated.  Thank you

[Altera_Forum]

When programming FPGAs, you pretty much have to "try it and see". 

 You might like to think in terms of XOR, AND, NAND, etc gates, but FPGAs don't really care about them. They care about mapping logic into their look-up tables (LUT), logic elements (LEs), or Adaptive Logic Modules (ALM), whatever the manufacturer has decided to call them.  For example, if I want to implement a huge multiplexer (implemented using lots of small muxes), and the FPGA has a 4-input LUT, and I want maximum speed, so plan on pipelining the multiplexer, then I know the "best" I can do is a 2:1 mux, since it has 3 inputs, i.e., the 2 input signals and the select. However, when I move to a different FPGA that has a 6 input LUT, I can create a 4:1 mux, since it has 6 inputs, i.e., 4 input signals and a 2-bit select.  Whether or not you use Altera's IP depends on whether you need to "encourage" the logic to use fast carry-chain resources (or some other secret-sauce resource). In the case of a compare, I would expect "if (a==b)" to work just as well as any alternative you can come up with.  Don't trust me though, try it yourself, look at the resource usage, and look at the RTL viewer to see how Quartus draws the circuit! :)  Cheers, Dave

[Altera_Forum]

FPGAs do not implement logic as gates but realises it in LUTs. Modern fpgas have aluts(adaptable) e.g. with 6 inputs. Thus if you just write in vhdl: 

out <= '1' when a = b else '0';  then this possibly translates to aluts as follows: 6 inputs alut is fed with 3 bits of (a) and 3 bits of (b) and resulting bit is configured in the alut locations according to equality. Thus 64/6 => 11 aluts are needed for first check. the 11 outputs are then checked again in cascade needing 11/6 => 2 aluts and a finl alut makes it 14 aluts overall.  if you use lpm_comapre then it tests more but if only use equality output then it will reduce to 14 aluts I believe.

[Altera_Forum]

Dave and Kaz,  

 Thanks a lot for your replies. As you noticed from my posting, I am familiar with "traditional" logic circuits, but FPGAs are new to me. Could you advise me on what books/websites to read or courses to take to learn more about how FPGAs are organized and how the synthesis process work? I think if I understand this my FPGA programming skills will improve a lot and I will be able to "encourage" (as Dave put it) the compiler to synthesize my circuit in a way that i consider best for the situation.  I look forward to your comments,  Shoys

[Altera_Forum]

I am not particularly experienced in reference material and I depend wholly on vendors descriptions. But you need really few things to switch to fpga if you are already familiar with general logic design. 

 The main theme in our post can be summarised as follows: using lpm is example of structural approach when you instantiate somebody else's work or your own lower work. using logic expressions is example of data flow or gate level and are dealt with by tool  using my vhdl expression is example of behavioral level when I leave it to tool to translate.  The above example also shows three layers of logic(aluts) which could compromise timing and registers may be needed between these levels in order to break long paths.

[Altera_Forum]

--- Quote Start ---   Could you advise me on what books/websites to read or courses to take to learn more about how FPGAs are organized and how the synthesis process work?   --- Quote End ---   The handbook for each FPGA describes its internal architecture. Take a look at the handbooks for a MAX II (CPLD), Cyclone IV or V (low-range FPGA), and Stratix IV or V (high-end FPGA), and you'll start to see differences. For example, look at the difference in DSP blocks between the Cyclone and Stratix series.  The Quartus GUI has a number of Netlist viewers that show you what you logic looks like and what resources it used. The Quartus hierarchy tab in the main display also shows you the resources used. When trying to see if Quartus "does what I ask", I look at the resources in the hierarchy tab to see if the design used the resources I expected.  I can't recommend any books on the subject, sorry. I would recommend just using the tools.  Cheers, Dave

[Altera_Forum]

What Dave said. 

I would also take a look at the "Quartus II integrated synthesis handbook" and, if you're really into it, the "Advanced Synthesis Cookbook". Other than that, I suspect that "literature" has a hard time keeping up with the continuous evolution of the synthesis tools and FPGA architectures.  One advice, valid for both FPGAs and custom silicon: Do not go aim straight for low level"optimized constructs. Modern synthesis tools can recognize a large number of common high level constructs and convert them into highly optimized designs. As kaz said, "a == b" is probably going to work out as efficiently as anything else you can write.  Sometimes, you'll find that the tools don't produce what you expect/need or that they're being unbelievably stupid and you need to get deep down into the details. But that's more the exception than the norm.

[Altera_Forum]

Dear Dave, Kaz and rbugalho, 

 Thanks for the replies. I already downloaded the references that rbugalho recommended. I am really interested in learning how the synthesis tools operate as I believe I will be more confident in my HDL programming and will be able to trust more the tools. A similar thing happened to me years ago when I took a "programming languages compilers design" class. What I learned there allowed me to see and do programming in a whole different way. Many assumptions were clarified, dumped or demystified. I believe I became a better programmer afterwards because I knew what the compiler would be doing. Of course, I also learned that I needed to understand the achitecture of the target microcontroller to design my programs around it. I am hoping the same will happen with the FPGAs and HDLs.  Thanks again for the advice. I will read through the references suggested, learn more about the architecture of the FPGA I am using (Cyclone) and at this time, since I have a close deadline for the project am working on, I will try to keep my code simple, well organized and documented and I will just trust the tool will give the optimal code.  Regards,  Shoys

[Altera_Forum]

--- Quote Start ---   I will try to keep my code simple, well organized and documented and I will just trust the tool will give the optimal code.   --- Quote End ---    The most important part of this sentence is the "well organized and documented", along with the design fits in the device and meets timing. The "optimal code" comment is ultimately irrelevant. Who cares if your design uses 10 more logic cells than optimal? The design works and you got it complete on time - that is ultimately what people (bosses, customers, etc) will care about.  I make this comment to help you focus on the important stuff :)  Cheers, Dave