Hi,
Based on my understanding, mSGDMA (Avalon-MM master) issues memory read/write requests. PCIe Hard IP receives these Avalon-MM transactions. PCIe Hard IP converts them into PCIe TLPs, sends them over the PCIe link. For incoming PCIe TLPs (targeting your FPGA), the PCIe Hard IP converts TLPs into Avalon-MM writes/reads, which mSGDMA can access. In common way, mSGDMA does not build or parse TLPs directly. Instead, it moves data to/from the PCIe Hard IP’s Avalon-MM or Avalon-ST interface. The PCIe Hard IP is responsible for converting Avalon-MM transactions into TLPs (and vice versa). I not sure if your previous implementation sound different or not.
Do I have to handle all TLP myself?? I don't have the experience for this, might not be realistic...
>> detail how the PCIe HIP handle the TLP , you may refer to the user guide under https://www.intel.com/content/www/us/en/docs/programmable/813754/25-1-1/introduction.html
I see online SSGDMA IP DMA PCIe... also only for Agilex 5??
>> At the moment we just enable the ssgdma for Agilex 5,
>> For Agilex 3 we will use MCDMA as instead , the Estimation Delivery Data will be around next year , please stay tune.
There is a PIO design example; even if it works, I also need tx bus mastering.
>> there is build in PCIe PIO example design in Quartus under IP catalog
>> also , PCIe GSRD on https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a3y135b.html
>> For tx bus mastering, we suggest to use MCDMA (to be release in future)
Hope that clarified
Regards,
Wincent_Altera
