Agilex 5 I/O voltage levels

[SDavi9]

For the Agilex 5 FPGAs for the HSIO banks their Supported I/O voltage standards are within the range of 1.0V - 1.3V. In my design if I have a choice of which standard to choose is there any benefits of which end of the range I should choose ? 

[ShengN_Intel]

Hi,

1.00 – 1.10 V (lower end):

Lowest I/O dynamic power, smaller voltage swing → reduced EMI and lower heat. Good for power-sensitive designs.

Practical when you want to minimize I/O power/emissions and traces are short, controlled, and low loss.

1.20 V (middle):

Good compromise: moderate power with larger voltage swing and better noise margins than 1.0–1.1 V. Broad compatibility with many vendor PHYs and SERDES termination schemes.

Practical when mixed systems where compatibility and reasonable power both matter.

1.30 V (higher end):

Largest signal swing and best noise margin (SNR), more tolerant for longer lossy traces, aggressive data rates (LVDS)

Practical when driving LVDS/legacy differential PHYs, long routes, or when you need maximum receiver margin for BER/jitter targets

Thanks,

Regards,

Sheng