Agilex 5 transceiver output clock

[Asaf_Bloch]

Hello Intel team,

We use the transceiver output clock, it CML format.

The CML output consists of a differential pair with

50Ω collector resistors, as shown in Figure 3

Is the Agilex-5 implement this 50Ω collector resistors and what is the VCC voltage?

When interfacing with differential CML receiver, do we need external components other than AC couple capacitors?

Thanks

Asaf

[WZ2]

Hi Asaf,

Thank you for your question.

Yes, the Agilex™ 5 transceiver CML output includes internal 50Ω collector resistors, so no additional external termination resistors are needed. When interfacing with a differential CML receiver, you only need to add AC coupling capacitors.

For recommended connection guidelines and further details, please refer to Intel's official Pin Connection Guidelines (PCG):

https://www.intel.com/content/www/us/en/docs/programmable/813266/current/pin-connection-guidelines-fpgas-and-socs.html

Best regards,

WZ