Agilex 7 FP32/FP16 TFlops performance calculation

[davidhorowitz]

Hello, 

I would like to calculate the following metrics for the Agilex 7 series:

-Peak FP32/FP16 FMA TFlops 

-Peak FP32/FP16 TFlops 

-Peak FP32/FP16 TFlops / mm^2 of fabric

How would I calculate these? 

I am also looking for the Local Memory Bandwidth, Memory Bandwidth, and die area of the part.

Can someone assist me? 

Thank you for your time!

[ShengN_Intel]

Hi,

Seem like a gpu problem. Could you post here https://community.intel.com/t5/Graphics/bd-p/graphics to get help?

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

Please ignore previous post.

Peak FP32/FP16 FMA TFlops:

Peak FMA TFlops = (Number of FP Units × Clock Frequency in GHz × 2)GFlops / 10^12

Peak FP32/FP16 TFlops:

Peak TFlops = (Number of FP Units × Clock Frequency in GHz)GFlops / 10^12

Peak FP32/FP16 TFlops / mm^2 of fabric:

TFlops/mm² = Peak TFlops / Die Area in mm²

Shows example for AGF027:

From here, https://www.intel.com/content/www/us/en/content-details/690880/agilex-7-fpgas-and-socs-f-series-product-table.html

can get total DSP is 8528, FP32/FP16 fmax is 750mhz/0.75ghz (refer here https://www.intel.com/content/www/us/en/docs/programmable/683301/current/dsp-block-specifications.html )

FP32 Peak FMA TFlops = (8528*0.75Ghz*2)GFlops/10^12 = 12.8TFlops

FP16 Peak FMA TFlops = 12.8*2 = 25.6TFlops

I'll research and post later the rest formula.

Thanks,

Regards,

Sheng

[davidhorowitz]

Thank you for your help! I will wait for the rest. 

[davidhorowitz]

Are peak TFLOPs the same for FP32 and FP16 ? These equations seem to suggest that. 

Disregard, I see that the equations are different. I mis-read. 

[AdzimZM_Intel]

Hi David,

For your question about local memory bandwidth, memory bandwidth and die area of the part, are you looking for M20K, MLAB or EMIF? Or another memory?

Regards,

Adzim

[davidhorowitz]

For die area, I'm asking for die area of the FPGA itself.

For my memory question, I would like the maximum bandwidth for the EMIF as well as M20K and MLAB. I understand that these numbers are dependent on multiple factors, but I'm looking for a highest performance type of metric. 

[davidhorowitz]

For DDR4 memory, i have this equation:

DDR4 Memory Bandwidth = (Data Rate (MT/s) * Bus Width (bits) * #channels ) /8

Based on the F-Series product table I calculated the DDR4 memory bandwidth as follows:

DDR4 Memory Bandwidth = (3.2) * 64 * 4) / 8  = 102.4 GB/s

Does this make sense? 

For the M20K and MLAB, I don't know what formula would be use to calculate bandwidth.

[AdzimZM_Intel]

Hi David,

For the die area, I think you can refer to FPGA package. For example:

• https://www.intel.com/content/www/us/en/docs/programmable/683458/current/fpgas-and-socs-f-series.html

Your calculation on DDR4 bandwidth should be okay.

For the embedded memory, you may refer to the link below:

• https://www.intel.com/content/www/us/en/docs/programmable/683241/25-1/embedded-memory-features.html
• https://www.intel.com/content/www/us/en/docs/programmable/683458/current/key-features-and-innovations-in-fpgas.html

Regards,

Adzim

[AdzimZM_Intel]

Hi David,

Did my previous reply have answered your questions?

Or you still got questions regarding that?

Regards,

Adzim

[AdzimZM_Intel]

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