Agilex 7 I-Series Dev Kit: PIPE Direct for custom PCIe/CXL controller?

[Dexter22]

Hi Intel Community,

I’m studying the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide and considering purchase of the Agilex™ 7 FPGA I-Series Development Kit (2× R-Tile, 1× F-Tile).

My research goal is to bypass the hardened PCIe/CXL controller and expose the PIPE 5.x SerDes interface into the FPGA fabric, so that I can run a custom soft controller (own LTSSM, EQ, DLLP/TLP, later extend to CXL.io → CXL.mem with 64B FLITs). Before purchasing, I’d like to confirm:

1. PIPE Direct availability

   • Does the I-Series Dev Kit expose R-Tile PIPE Direct to the fabric (via EMIB), enabling a full soft PCIe/CXL controller?

   • Any board-level constraints (e.g., octet-wide Gen5 base mode, per-lane Rate2:0/Powerdown1:0 controls)?

2. Tool/flow support

   • The User Guide notes that Quartus Pro 21.2 had no example/testbench for PIPE Direct. What is the current Quartus Pro version recommended?

   • Are there any reference stubs or app notes for PIPE Direct (Tx/Rx wrapper, reset/clocking examples)?

3. Root Port / Endpoint configs

   • Any guidance on PERST#, equalization sequencing, retrain, refclk selection when not using the hardened controller?

4. CXL hybrid approach

   • If I start with CXL.io only, is it possible to use the hardened PCIe IP just for link/LTSSM while running custom DLL/TLP/CXL layers in soft logic? Or does any custom higher-layer implementation require going fully PIPE Direct?

5. Board I/O

   • Which ports (x16 edge connector, MCIO/SFF-TA-1016) are usable in PIPE Direct mode? Any pinout or kit-specific notes?

   • specifically: if I connect through the edge connector (to a host system), can I still operate the R-Tile in PIPE Direct mode with my soft controller, or is PIPE Direct limited to MCIO breakout only?

6. Validation environment (important)

   • I have access to a CXL-capable host (Sapphire Rapids) but no PCIe/CXL protocol analyzer.

   • Is it realistic to debug link training and equalization in PIPE Direct without an analyzer? If yes, what tools/flows are recommended (ILA debug, Quartus monitors, logging)?

   • Would you recommend starting with two Agilex kits back-to-back instead of host-only, given that I don’t have an analyzer?

   • Are there any Intel or third-party reference setups for early CXL bring-up without protocol analyzers?

I’d greatly appreciate any application notes, example projects, TCL scripts, or checklists to help with PIPE Direct bring-up.

Thanks in advance!

[RongYuan]

Hi,

You can generate examples from CXL IP in the latest Quartus Pro 25.1.1, with new added M-series FPGA. PCIe and CXL are two different IPs in the tool. CXL IP requires a license and its user guide is restricted to NDA users only. Please contact your local Sales or Distributor for more info.

The most basic CXL type is Base HIP. The PIPE mode is for simulation only.

The CXL uses R-Tile so current example designs are available for below two dev kits. The M-series dev kit requires MCIO cable.

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

The CXL test is heavily relied on a dedicated software, even checking the LTSSM. So you basically don't need a protocol analyzer.

Regards,

Rong