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Agilex DDR4 Signal Integrity Simulations Over Shoot - Undershoot Limit and Target Impedance

emrahener
Beginner
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Hi,

We are working on a digital board design with Agilex FPGA and Discrete DDR4 memories.  I have made simulations for DQ traces and still working on other connections. 

Although a 40 Ohm trace is suggested in ug-ag-emi-683216-743630 my results show selecting 34 Ohm traces for DQ nets results in a better performance  for 3.2 Gbps.

I am comparing the two cases :

CASE-1

FPGA : Pod12_io_s0r34c 

DDR4 : DQ_34_3200

Traces : 34 Ohm 

CASE-2 

FPGA : Pod12_io_s0r40c 

DDR4 : DQ_40_3200

Traces : 40 Ohm 

I attached obtained results and 34-40 Ohm comparison is on slides 6-13

34 Ohm case seems to have a better performance. Can you comment on this?

DDR Manufacturer datasheet provides a constraint on overshoot- Undershoot of the signal on device pin.

Since There is some Overshoot up to  1.33881 V and undershoot up to -0.205288V @ FPGA . Can you also provide a limitations for the overshoot -undershoot for FPGA.

 I tried several trace impedances however those out of 0V-1.2V range waveforms seems to be un avoidable.

 

 

 

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AdzimZM_Intel
Employee
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Hello emrahener,


Thank you for submitting your question in Intel Community.

I'm Adzim from Penang Global Application Engineer will assist you in this thread.


"34 Ohm case seems to have a better performance. Can you comment on this?"

I have checked your results and I agree with your opinion because the 34 Ohm case has better margin compared to 40 Ohm case.

The user guide has provided the guideline for user to create the routing for EMIF.

There are some general requirement that need to follow when doing the routing and it's limit to the trace.

I believed that the user can perform the simulation to get the optimum result.


"Since There is some Overshoot up to  1.33881 V and undershoot up to -0.205288V @ FPGA . Can you also provide a limitations for the overshoot -undershoot for FPGA."

You should be able to find the details in Agilex Device Data Sheet in the Maximum Allowed Overshoot and Undershoot Voltage section.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/maximum-allowed-overshoot-and-undershoot.html


Regards,

Adzim



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AdzimZM_Intel
Employee
310 Views

Hello emrahener,


Thank you for submitting your question in Intel Community.

I'm Adzim from Penang Global Application Engineer will assist you in this thread.


"34 Ohm case seems to have a better performance. Can you comment on this?"

I have checked your results and I agree with your opinion because the 34 Ohm case has better margin compared to 40 Ohm case.

The user guide has provided the guideline for user to create the routing for EMIF.

There are some general requirement that need to follow when doing the routing and it's limit to the trace.

I believed that the user can perform the simulation to get the optimum result.


"Since There is some Overshoot up to  1.33881 V and undershoot up to -0.205288V @ FPGA . Can you also provide a limitations for the overshoot -undershoot for FPGA."

You should be able to find the details in Agilex Device Data Sheet in the Maximum Allowed Overshoot and Undershoot Voltage section.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/maximum-allowed-overshoot-and-undershoot.html


Regards,

Adzim



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AdzimZM_Intel
Employee
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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