Alter Beginner

[Altera_Forum]

Dear friends 

I am altera beginner,i want to know that,what is top level entity?,Then one more problem i wrote on vhdl code ,code is this library ieee;  use ieee.std_logic_1164.all;  entity half_adder is  port (x,y,p,q :in bit;  z,r :out bit );  end half_adder ;   architecture adder of half_adder is  component and1  port(a,b :in bit;  c:out bit);  end component;  component xor1  port(e,f:in bit;  g:out bit);   end component;   begin   n1:and1  port map(x,y,z);  n2:xor1  port map(p,q,r);   end adder;   it shows the error like that Error: Node instance "n1" instantiates undefined entity "and1" Error: Node instance "n2" instantiates undefined entity "xor1" i don't want what is this,This error cccurs when this module is treated as a top level module.this is one module of the project,if a treat other module as a top level entity there is no error,pls can anybody make me understand what's happening there. regards  hareesha

[Altera_Forum]

Think of the components as belonging to a tree (hierarchy). 

 xor1 and and1 are sub components of half_adder  i.e. They are parts of your design and must be compiled along with the top level.  If you use xor1 or and1 as your top level then they probably do not depend on any other components.  For your system to compile fully, you need to compile the top level and all it's sub components. i.e. half_adder, xor1, and1

[Altera_Forum]

There's some useful info here if you're new to VHDL: 

 http://www.doulos.com/knowhow/vhdl_designers_guide/

[Altera_Forum]

--- Quote Start ---   what is top level entity?  --- Quote End ---     A top level entity is the part of the design that calls other design entities in its design structure. For example, you have entities A, B and C. Further, A uses B and C in its design (and so instantiates them in its design) while B and C are completely independent designs not calling any other entity. Then A is the top-level entity.    It is possible that your project may have two designs, say X and Y, which may instantiate some sub-entities (A, B and C), but may not instantiate each other. In that case, two hierarchical structures exist in your project and you must specify which is your top-level entity. Should you choose X, you will not be able to incorporate Y in your project and vice versa. If there is no way X and Y are related to each other, they may form two separate projects.     --- Quote Start ---   Then one more problem i wrote on vhdl code ,code is this library ieee; use ieee.std_logic_1164.all; entity half_adder is port (x,y,p,q :in bit; z,r :out bit ); end half_adder ;  architecture adder of half_adder is component and1 port(a,b :in bit; c:out bit); end component; component xor1 port(e,f:in bit; g:out bit);  end component;  begin  n1:and1 port map(x,y,z); n2:xor1 port map(p,q,r);  end adder;   it shows the error like that Error: Node instance "n1" instantiates undefined entity "and1" Error: Node instance "n2" instantiates undefined entity "xor1" i don't want what is this,This error cccurs when this module is treated as a top level module.this is one module of the project,if a treat other module as a top level entity there is no error,pls can anybody make me understand what's happening there. regards  hareesha  --- Quote End ---     A very common error for the beginners. Now your program is ok except that it doesn't specify where exactly the compiler should find the entities like and1 and xor1. I suppose you assumed they are available in ieee.std_logic_1164.all package. However what is available in this package is only 'and' or 'xor' (note the absence of index '1' here). Moreover, and and xor are available as functions so instead of using them as entities, you can very well write lines like  z <= x and y; and  r <= p xor q; in your program.

[Altera_Forum]

Thanks for your reply,ya you r telling is exactly wright ,i know i can use functins and xor,so if i define and1 and xor1 in user defined packages Is this problem can be solved?

[Altera_Forum]

--- Quote Start ---  Thanks for your reply,ya you r telling is exactly wright ,i know i can use functins and xor,so if i define and1 and xor1 in user defined packages Is this problem can be solved?  --- Quote End ---     Yes (though you don't need to do that; just use the functions).