Altera Max II unable to detect voltage levels correctly from a incoming signal

[Altera_Forum]

Hello everyone, 

 I'm new to this forum and would like to apologize if I'm posting a question that has already been asked by another person.  I've been running into this problem during my development of an RFID system using 13.56 MHz using the Altera Max II. I'm using Verilog as the HDL to program the Altera Chip. I'm currently trying to read a sub-carrier signal at a rate of 847 KHz with using my altera Max II. When I use a 50 MHz clock signal to sample that input and then output it back out to the scope, I see a clear and exact replica of my input signal without a problem.   The problem is when I try to perform some simple logics using the Posedge of the input signal, it does not seem to be detecting the input positive edge correctly. The input signal aren't continuous and only happens for able 1 millisecond. Below are a few things that I've tried:  -Using the 50 MHz signal to sample the input and store that as a register, then using that register to trigger my code for the positive edge. The same problem was still occurring, which led me to think that the code was the issue.  -I then used the same code but instead of inputting a the regular input, I generated the signal from a function generator with a similar Voltage levels and frequency as my input. But it is continuous instead of only for a short period of time. The result being that the code does trigger on that positive edge, which shows that there wasn't anything wrong with me reading in the input signal but instead something is screw up with the way I read in the input for the non-generated signal.   I was wondering if anyone had encountered this issue. If there's a standardized way of denoting the I/O for the Altera Chip. I'm currently using LVTTL input because the voltage levels I'm currently looking at is 3.3 V. Please let me know if you want me to provide any more information.  Thank You in advance everyone,

[Altera_Forum]

If you are new to FPGA/CPLD programming, you may not realize that you should have ... 

 1. HDL describing your synthesizeable design  2. HDL testbench that exercises your synthesizeable logic  3. Pin assignments for your FPGA/CPLD  4. Timing constraints for your FPGA/CPLD  It sounds like you have (1) and (2), but have probably not implemented (2) or (4).  First implement a simulation, and that way, you can ask questions while showing how you think your design is supposed to work.  Assuming you'll initially ignore that recommendation :), make sure you add timing constraints, so that Quartus can provide feedback to you.  If you see any warnings in the Quartus messages console, then you need to pay attention to them.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  If you are new to FPGA/CPLD programming, you may not realize that you should have ...  1. HDL describing your synthesizeable design  2. HDL testbench that exercises your synthesizeable logic  3. Pin assignments for your FPGA/CPLD  4. Timing constraints for your FPGA/CPLD  It sounds like you have (1) and (2), but have probably not implemented (2) or (4).  First implement a simulation, and that way, you can ask questions while showing how you think your design is supposed to work.  Assuming you'll initially ignore that recommendation :), make sure you add timing constraints, so that Quartus can provide feedback to you.  If you see any warnings in the Quartus messages console, then you need to pay attention to them.  Cheers, Dave  --- Quote End ---    Dave,  Thank You for your reply. I did [1] , [2], and [3]. I started learning Verilog and started writing small programs. Then I drive into developing code for my project. I started off using Quartus Model Sim to simulate my code. Everything works correctly and well and good with my simulated code, which included my testbench and everything. But when I went to synthesize my code it was a bit tough because timing isn't always consistent for my input signal. The input signal also has a slight difference in duty cycle, which made my logic a lot more complicated than it was when I simply try to model the input signal.   The one thing that I didn't do is add timing constraint into Quartus to make sure my compiler flags me when. The one thing that I see from my compilation that concerns me a bit is the Data Delay. I've attached an image that shows the log I get from the TimeQuest Timing Analyzer. Please let me know what you think about that and if it would have anything to do with my problem. The variable DataIn_Test is my input signal where the mBPSK_Clk is a signal I try to generate using my input signal.  Thanks in advance Davehttps://www.alteraforum.com/forum/attachment.php?attachmentid=8535

[Altera_Forum]

Provided thje input signal meets the specifications (level, maximum risetime), the problem is probably in the logic. 

 But you did neither clarify the input signal characteristics (e.g. by posting a waveform) nor posted your logic.