Altera PLL Zero Delay Buffer Mode

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Altera PLL Zero Delay Buffer Mode

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What is the correct way to use the zero delay buffer mode in the Altera PLL function in Quartus v15.0? The parameter window doesn't have a selection of which output clock this is applied to like it used to have. In fact, it adds an I/O pin to the symbol, but doesn't indicate what frequency output clock is applied to that pin. The user guide for the Altera PLL is not clear regarding this either. Any help anyone can provide would be appreciated.

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