Altera RAMB4_S4_S4 generic map problem?

[Altera_Forum]

hello, 

I am learning the cpu_lecture from opencores with my cycloneII board, I replace the xilinx RAMB4_S4_S4 IP core into altera one, but the design need 8 rams with different contents, and it is filled with generic map, but the altera ram can not do that, just can fill a .hex file, so please help me with some tricks. regards :eek:

[Altera_Forum]

Using initialization hex files shouldn't be too hard, but may be unwanted to keep the code compatible. 

 It should be possible to design a RAMB4_S4_S4 wrapper including the INIT generics, except for the non-existing RST inputs, by using an inferred DP RAM with initialization.