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Hello friends,
Am a student new to Quartus and Altera devices. Am working on my project and it would require an unstable voltage supply (at START) to my stratix III FPGA. This i will compare with a preset voltage level at REF as shown in the attached file. I like to know if the board has the facility for voltage variation or do u suggest using an alternative voltage source (e.g voltage regulator) to produce an unstable supply to the board (not too sure about that, dont want to fry ma board). In addition, how can i come about setting a precise voltage for the REF using VHDL (structured)... i want to believe the language has that capacity.Link Copied
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