When i use a lvds ip core there is an odd error, and there is no clock output from the lvds module. Andbody who has met this before? 3Q
Warning: PLL cross checking found inconsistent PLL clock settings:
Warning: Node:altlvds_tx_component|auto_generated|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 1.953
Warning: Node:altlvds_tx_component|auto_generated|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 1.953
Warning: Node:altlvds_tx_component|auto_generated|pll|clk[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 1.953
