Any ideas why this code isn't working

Altera_Forum · ‎10-21-2009

Backgroung, working with Terasic DE1 kit

Trying to grab serial data from Copernicus Chip, interface

http://www.sparkfun.com/datasheets/G...cus_Manual.pdf

by default chip should give us $GPGGA once a second

the important details I have commented in the code, which runs on a 27m clock

GPSin is the TXA pin from the chip, pps is the pulse per second pin

Altera_Forum · ‎10-21-2009

By using Verilog part select expressions, most of your text collapses to a few lines, e.g.:

gpstream<=bitstreamin;

Generally, it can't be seen, if your code uses an edge sensitive always block as required. So you may want to throw away the bitwise assignment garbage and show the overall structure, too.

Altera_Forum · ‎10-21-2009

Yes I Am writing this under a posedge block with a 27m clock, the other pArts relating to the LCD are working. I can give you more info later, typin this response on my wifes iPhone while she drives

Altera_Forum · ‎10-21-2009

It seems like your treating the UART bitstream as synchronous 8 bit data stream, but it isn't. It has at least one stopbit and one startbit after 8 data bits, it uses basically a 10 bit frame.. Furthermore, it's not guaranteed, that the individual character frames are transmitted continuously. Instead, the UART receiver is expected to synchronize on each start bit a new. See http://en.wikipedia.org/wiki/uart for a brief explanation.

Altera_Forum · ‎10-22-2009

Hey, thanks for saying you can see what I am tryin to do, the PDF tell me we have

Baud Rate 38.4 K

Data Bits* 8

Parity* None

Stop Bits* 1

Flow Control * no

But no informatoin on the start bit, but you said there has to be one.

Sorry If it looks messy, been out of development for decades, working alone on this. Mucho mucho thanks for your help FVM

I see what you mean, we may get $...G......P..G....................G..A

instead of $GPGGA

Altera_Forum · ‎12-09-2009

FVM, take a look and give your opinion,do you feel I am getting closer???

Trust me, I appreciate your help, I am having a blast learning this stuff

// running under posedge 27mhz clock on Terasic DE1

// working now with venus Venus634LPx unit

// info at http://www.sparkfun.com/commerce/product_info.php?products_id=9133

// coperniucs unit quit, reason unknown

// buad rate is now 9600

// when we are not in a byte (uartf=0) and GPSIN goes low

if (uartf==0 & GPSIN==0)

begin

uartf<=1;

bitstreamin<=0;

bitcount<=0;

bitqueu<=bitqueu << 8;

// shifting queu left 8 bits to make space for new byte

end

if (uartf==1)

begin

if (bittimer!=2812) bittimer<=bittimer+1;

if (bittimer==2812)

begin

bitstreamin[10]<=bitstreamin[9];

bitstreamin[9]<=bitstreamin[8];

bitstreamin[8]<=bitstreamin[7];

bitstreamin[7]<=bitstreamin[6];

bitstreamin[6]<=bitstreamin[5];

bitstreamin[5]<=bitstreamin[4];

bitstreamin[4]<=bitstreamin[3];

bitstreamin[3]<=bitstreamin[2];

bitstreamin[2]<=bitstreamin[1];

bitstreamin[1]<=bitstreamin[0];

bitstreamin[0]<=GPSIN;

bittimer<=0;

bitcount<=bitcount+1;

end

// when bitcount gets to 10 we add it onto the que

// bit order reversed because UART gives us LSB first, MSB last

if (bitcount==10)

begin

uartf<=0;

bitcount<=0;

bitqueu[0]<=bitstreamin[9];

bitqueu[1]<=bitstreamin[8];

bitqueu[2]<=bitstreamin[7];

bitqueu[3]<=bitstreamin[6];

bitqueu[4]<=bitstreamin[5];

bitqueu[5]<=bitstreamin[4];

bitqueu[6]<=bitstreamin[3];

bitqueu[7]<=bitstreamin[2];

end

Altera_Forum · ‎12-09-2009

After detecting the falling edge of the start bit, the first delay has to be a half bit time, because the data has to be sampled at the nominal center.

There are dozens (or hundreds?) of Verilog and VHDL UART examples in text books and on the internet. Some have been posted at Altera Forum. You can try to adapt an existing one, but it's of course instructive to design your own.

Two remarks on your coding style:

You can save of lot of text by using more intelligent Verilog constructs:

bitstreamin <= {bitstreamin, GPSIN}; // assuming a decreasing bit index

or use a loop for the assignment of multiple bits

Altera_Forum · ‎12-09-2009

Thanks for understanding I want to hammer at this till it works and not use someone elses code. For your wisom and generosity, I shall have the forum admins promote you from "FVM" to "Darth FVM". Please tell us more about invoking the "verilog part select"

Altera_Forum · ‎12-13-2009

Thanks for info FVM, I am now reading the time off the $GPGGA string sucessfully, maybe in a few days when I can read my coordinates from there I can post them on this forum so you can send someone to rescue me from this island.