Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18464 Discussions

Are divided clocks synchronous with the source clock?

jch4416
New Contributor I
196 Views

Hello,

I am working on a rather slow (1.8432MHz master clock) cpld design. There are 4 clocks that I generate by dividing the master clock by different integers. The divisions are done with synchronous counters, so the edges of each generated clock should be synchronous with the master but delayed by one clock to q time.

Are the resulting clock domains not considered synchronous? Does the data from one domain require synchronization when being used by another even when the clocks are related as I explained?

I realize this is a newbie question, but I've been an analog and power guy for the last 15 years without doing much digital design.

Thanks,

Jim

 
0 Kudos
5 Replies
JonWay_C_Intel
Employee
184 Views

The data require synchronization or not depends on what clock you use.
If you launch with CLKA, and latch with CLKB.
CLKA and CLKB are different source or different phase then yes, you need to synchronize the data.

For your reference: https://www.youtube.com/watch?v=0A9mtv2GkII

 

jch4416
New Contributor I
171 Views

Thanks JonWay_C. I think that despite the many voices out there saying that a (synchronously) divided clock is synchronous with its source, that it is not in a strict sense because of the variation in the Tco parameter. What I was seeing was hold time violations on data from the divided clock domains going to the source clock domain. This sort of makes sense when you look at the edge of the divided clock being one Tco behind the source, and then the data from the divided domain being one Tco behind the divided clock edge. - providing 2*Tco_max < Th_min. Weird that the EPM family datasheet says that hold time is 0 though.

I was able to fix the violations by using the negative edge of the source clock to clock data from the divided domains. The positive edges of the divided clocks were one Tco behind the positive edge of the source clock and the source clock is very slow (T = 542ns), so there should now be ~270ns of setup and hold time for the data from the divided domains.

Now I get a warning about that I shouldn't be using both edges of the source clock:

(Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.
Warning (308010): Node "cpld_master_clock"

Is this really something I should worry about?

JonWay_C_Intel
Employee
160 Views

I think the question has evolved into a timing closure question.

Can you file a new forum case referring to this one, so that my colleague specializing in timing closure can look into this?

Once you have created a new thread, can you update the new forum thread link in here. Thanks.

 

jch4416
New Contributor I
152 Views

Hello JonWay. I createda new post as you suggested. The title is:

"Timing Closure for domain crossing between source and divided clocks"

JonWay_C_Intel
Employee
135 Views

Thanks. My colleague specializing Timing Closure will assist you.

Reply