Are there any issues in sim models of ALT_LVDSRX with DPA?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Are there any issues in sim models of ALT_LVDSRX with DPA?

1,310 Views

I have a simple simulation env where I send a constant pattern serially to the ALT_LVDSRX w/DPA instantiation in my design. I see that the DPA has locked. But then every 150 or so pixel clocks, it looks like the DPA phase is readjusted. I do not vary any thing in the test bench so this puzzle me? The test pattern I send is also a 14 bit stream of 1010. So there are more than 256 transitions for the DPA to lock.

Any one have experience with this and can shed some light?

Thank you in advance.

Best regards,

Sanjay

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.