Quartus Prime 15.1, Aria 10, IOPLL problem
In Qsys I set IOPLL outclock1 (loaden[0]) to 125MHz , but when I compile the design it shows
that loaden[0] is 156.25MHz instead of 125MHz !
IOPLL reference clock frequency is 125MHz. I also set outclock1 (lvds_clk[0g]) to 1250MHz and
outclock2 (LVDS Core Clock) to 125MHz and it looks that those 2 clocks are correctly set.
Fitter and Timequest has such report :
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Clock: IO_PLL_inst|iopll_0|altera_pll_i|twentynm_pll|iopll_inst|loaden[0] was found on node: IO_PLL_inst|iopll_0|altera_pll_i|twentynm_pll|iopll_inst|loaden[0] with settings that do not match the following PLL specifications:
Warning (332056): -multiply_by (expected: 10, found: 25), -divide_by (expected: 10, found: 20)
Warning (332056): Node: IO_PLL_inst|iopll_0|altera_pll_i|twentynm_pll|iopll_inst|lvds_clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 8.000
Warning (332056): Node: IO_PLL_inst|iopll_0|altera_pll_i|twentynm_pll|iopll_inst|outclk[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 8.000
How could I set loaden[0] to correct frquency 125MHz ?
Regards: Janez Dolenc
