I have a broad with an arria 10 FPGA (10AX066N2F40), using a 2.5V VCCIO for 3V I/O bank 2L, and bank 2L connects directly to a MCU supplied by a 3.3V power.
It mentions that VIH max=3.3V when VCCIO=2.5V in the Arria 10 datasheet (Table 14. Single-Ended I/O Standards Specifications),
but when I run a project that MCU output to bank 2L input, the voltage of VCCIO 2.5V power rail becomes 2.7V instead of the initial voltage 2.5V.
The bank 2L can receive the 3.3V logic levels normally,
but it seems that, the MCU's 3.3V output leaks through the clamp diode in FPGA, get a voltage drop (aprox. 0.6V), then drop to 2.7V, and the 2.5V VCCIO supply doesn't have the function of current sink, result in 2.7V present.
Is anything wrong? Thanks!
Hi @XWang134 Do you mean if the MCU change to 0V, VCCIO will also return to 2.5V?
It is better that the VCCIO do not exceed 2.65V as specified in datasheet. Table 3. Recommended Operating Conditions for Intel® Arria® 10 Devices
Also, as https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd... mentioned: Arria 10 devices do not have on-chip clamping diode.
Here is what you can try:
1) Use an external clamping diode. I would expect that 2.5V + Vclamp lets say is 0.6V = input clamped to 3.1V. See if the VCCIO is better.
2) Check your regulator circuitry. By right, regulator regulates your VCCIO, and shouldnt be stable at 2.7V.
Yes, VCCIO return to 2.5V after MCU output disabled.
I see it is abnormal while VCCIO pull to 2.7V, but I can't find where the leakage is, all other components powerd by both 2.5V and 3.3V is removed from the board.
I tried that solder a resistor (200 Ohm) acorss VCCIO and GND, for emulating a lite load, then 2.7V came down to 2.6V.
It seems that the regulator of VCCIO 2.5V have not the function of sink current.
I could set the 3.3V down to 3.2V, and set the 2.5V up to 2.6V, avoid doing modification of PCB, and bring VCCIO to safety zone.