Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Arria 10 AS x4 Mode

Fresh_Leon
New Contributor I
489 Views

Dear, Sir

 

We know that AS x4 mode and x1 mode can be configured by MSEL pin.

 

Fresh_Leon_0-1681117279095.png

 

x4 and x1 AS mode share the same MSEL pin.

 

Question is: how does FPGA know it should boot with x1 bit width or x4 bit width ?

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FvM
Valued Contributor III
477 Views

Hello,
please avoid cross-posting of the same question in multiple forums.

x4 AS mode is set in the configuration stream, specified in Quartus Device and Pin Options. Configuration read starts always in x1 mode. If x4 mode setting is found in the image, the configuration logic switches to x4.

Regrads

Frank

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NazrulNaim_Intel
Employee
456 Views

Hi,

 

Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings.

 

Thank you for your patience.

 

Best Regards,

Nazrul Naim


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NazrulNaim_Intel
Employee
420 Views

Hello,


As per 'FvM' have replied. The reply can be accepted as answer. 'Configuration read starts always in x1 mode. If x4 mode setting is found in the image, the configuration logic switches to x4.'


Hope that answers your question.


Regards,

Nazrul Naim


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NazrulNaim_Intel
Employee
392 Views

Hi,


As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards,

Nazrul Naim


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