Looking for suggestions on how to proceed with a tough issue. We want to support DDR4 in future products so we added it to our board designs and FPGA pinout long before my tenure. The board design was not simulated but careful design techniques were used for the DDR4 interfaces. Both banks share the same power supply.
The FPGA is a 10AX016E3F29E2SG.
1. Two independent interfaces, 32 bit data width (4x DDR4 by
2. 933 Mhz (DDR4-1866).
3. DDR4 bank 0 occupies FPGA banks 2J and 2K. DDR4 bank 1 occupies FPGA banks 3A and 3B.
4. I designed a memory checker built around LFSR. It runs on emif_usr_clk which is 233.25 Mhz.
Bank 0 has intermittent bit failures during LFSR test. Bank 1 never fails. The bit failures occur during writes. Both banks always calibrate fine.
Experimenting with ODT termination values in the IP core seems to have no effect but that may be masked by the fact changing the termination changes the build result. I can change seeds with a given termination and get some builds that work overnight and some builds that fail every LFSR pass. Most of the builds don't work. The same is true if I keep the seed constant and try different terminations.
The FPGA always makes timing, the DDR timing report always looks good and the external memory interface toolkit shows calibration numbers are very close between the two DDR4 banks. Read margins on bank 0 are about 20 ps smaller but yet it is writes that fail.
The write and read windows for both banks are around 400 ps.
I am not sure how to proceed.
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Thank you for providing your issue in details.
So now you have two identical DDR4 memory interface in a design. The Bank 0 has issue but Bank 1 is fine.
Regarding to the issue, do you see any symptom that can cause the failure? Any specific transaction that will fail?
Have you tried to test the Bank 0 alone in a design?
Like making a design with one interface only.
If that possible, can you observe the result?
Can you test the board design with EMIF example design for each interface?
Please let me know if you need help to create the design. Thank you.
Hi Adzim. The issue has been resolved and was not a DDR4 problem but was a timing issue during write data generation.
Both interfaces appear to be working fine now.