Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19493 Discussions

Arria 10 EMIF Register configuration to trigger write to Memory components’ Mode Reg

Altera_Forum
Honored Contributor II
892 Views

Hi 

 

We are using Arria 10 EMIF. We need to control the memory components’ mode register settings through Controller Register Writes. Please let us know the sequence of Controller register write to initiate write to Memory components’ mode register (MRS0-MRS6). 

 

Thanks & Regards 

S.T.Saraswathy
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
162 Views

This gets configured in the EMIF controller parameter editor when you add the controller through the IP catalog or in Qsys. It's handled automatically by the controller during memory initialization. See this online training: 

 

https://www.altera.com/support/training/course/omem1122.html
Altera_Forum
Honored Contributor II
162 Views

Hi  

 

Thanks sstrell. The section 3.4.1 of "JEDEC DDR4 SDRAM Specification" says that "Mode Registers can be altered by re-executing the MRS command during normal operation." In case if I want to do the same in my simulation (i.e rewrite to MR register after initialization), how can I achieve it in Arria 10 EMIF Simulation Setup 

 

Thanks & Regards 

S.T.Saraswathy
Reply