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Altera_Forum
Honored Contributor I
980 Views

Arria 10 IOPLL output not synchronous with input

I'm using an IOPLL on the Arria10. I really need a 2x synchronous clock with my input, but i cannot get any synchronous output (well sometimes I can but its rare). In the attachments, this is the same test points, the blue clock is my IOPLL input clock, the yellow is the 2X output. What you see in the attachments is three different JTAG loads of my project, I get a different alignment each time.  

 

I've tried Normal, Source Synchronous, and direct modes, none of which consistently yield a synchronous output. I need those edges to align. Am I wrong in expecting them to be synchronous? I don't see any other PLL options in the Arria 10 library, all the other PLLs are dedicated to gigabit transceivers either in PCI, Ethernet or vanilla transceivers. 

 

Thanks
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5 Replies
Altera_Forum
Honored Contributor I
82 Views

Hi mike, 

 

1.Can you use signal tap and check it. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
82 Views

How do you do that when one of the clocks is the one I'd have to use to clock signaltap? Besides, I can see it on a scope, and the two signals come up different every time.

Altera_Forum
Honored Contributor I
82 Views

Hi mike, 

 

 

--- Quote Start ---  

How do you do that when one of the clocks is the one I'd have to use to clock signaltap? Besides, I can see it on a scope, and the two signals come up different every time. 

--- Quote End ---  

 

 

Kindly Check the below image attached. 

In image we have one signal that is having frequency of 1kHz(red color), which is generated by 10Khz. And ticks at top of signal tap are generated by clock frequency/sampling clock(10Khz). which we gave in signal taps clock field. 

And in image we can see the change in output clock with respect to the input clock(Rising-edge). 

 

 

--- Quote Start ---  

Besides, I can see it on a scope, and the two signals come up different every time. 

--- Quote End ---  

 

Yes, we can use if oscilloscope is calibrated and probes are working fine. Even if, It is calibrated we will have small phase shift which is not noticeable.In your case we dont know it is because of oscilloscope,probe or coding. 

So only i suggested for signal tap. 

During debug it will be helpful. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
82 Views

Hi mike, 

 

 

--- Quote Start ---  

How do you do that when one of the clocks is the one I'd have to use to clock signaltap? Besides, I can see it on a scope, and the two signals come up different every time. 

--- Quote End ---  

 

 

Kindly Check the below image attached. 

In image we have one signal that is having frequency of 1kHz(red color), which is generated by 10Khz. And ticks at top of signal tap are generated by clock frequency/sampling clock(10Khz). which we gave in signal taps clock field. 

And in image we can see the change in output clock with respect to the input clock(Rising-edge). 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14320  

 

--- Quote Start ---  

Besides, I can see it on a scope, and the two signals come up different every time. 

--- Quote End ---  

 

Yes, we can use if oscilloscope is calibrated and probes are working fine. Even if, It is calibrated we will have small phase shift which is not noticeable.In your case we dont know it is because of oscilloscope,probe or coding. 

So only i suggested for signal tap. 

During debug it will be helpful. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
82 Views

Hi Mike, 

 

Let me first state that its difficult to synchronize an external clock with a PLL generated clock. This is due to the PLLs inherent design. PLLs are Analog/Digital blocks which have feedback loops inside. Thus when a PLL locks onto a clock and begins to generate its own derived clocks.. there will be some amount of delay introduced which will cause a shift in the output clock with reference to the input clock. It may be possible to correct this at times (depending on the PLL implementation in the FPGA) using jitter or phase shift mechanisms.  

 

For most designs where the generated clocks have to be synchronized with the source clock, the solution is to generate another clock with the same frequency and time parameters as that of the input clock along with the generated clocks. You can then have the PLL synchronize the generated clocks to their respective edges. This way you will have two clocks that are synchronous to each other in phase with one being exactly same frequency as that of the input clock.  

 

For example,  

Input clock to PLL = 25MHz 

Desired output clock1 = 100MHz 

Desired output clock2 = 150MHz , both these clocks need to be synchronous with the input 25MHz clock.  

 

The way to achieve this is have the PLL generate all 3 clocks : 

 

Input clock = 25MHz 

O/p clock1 = 25MHz 

O/p clock2 = 100MHz 

O/p clock3 = 150MHz 

 

Then set the PLL to synchronize all three output generated clocks in phase and use Jitter correction if needed. This way you will have the synchronous clocks you need for the design. Hope this helps!
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