Arria 10 core PLL error 15744

Altera_Forum · ‎09-16-2017

I'm getting the following error when instantiating a generated Arria 10 core PLL (fpll_inst):

   Error (15744): The settings must match one or more of these conditions: 
    Error (15744): ( prot_mode == UNUSED ) OR ( pllcout_enable == PLLCOUT_DISABLE ) OR ( m_cnt_in_src == M_CNT_IN_SRC_CSCD_CLK ) OR {((vco_freq_hz-7'h64)<=(cnt_div*f_out_c2))}
    Error (15744): But the following assignments violate the above conditions: 
    Error (15744): prot_mode = BASIC_TX
    Error (15744): f_out_c2 = 12135922
    Error (15744): vco_freq_hz = 5000000000
    Error (15744): pll_c2_pllcout_enable = PLLCOUT_ENABLE
    Error (15744): pll_c_counter_2 = 412
    Error (15744): pll_c_counter_2_in_src = M_CNT_IN_SRC_PH_MUX_CLK

Looking into the qsys file I see that

<parameter name="gui_hssi_prot_mode" value="0" />

But in the xml file generated from the qsys file I observe:

<parameter name="prot_mode" value="basic_tx" />

How can I control this parameter, or the others to satisfy the requirements?

Altera_Forum · ‎09-18-2017

This seem to be resolved by upgrading to v17.0.2.602.