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Altera_Forum
Honored Contributor I
1,054 Views

Arria 10 spine clock region overused

Hi, 

 

I'm trying to build a fimware with several transceiver banks. If I use 4 banks, it's fine. But 5 banks cause congestion in the "spine clock region" and the compilation sits in "IO Placement" for about an hour and eventually gives up with the follow error (my guess at the relevant part is highlighted in red). I've not see this error before. Any thoughts would be appreciated. 

 

 

Error (14996): The Fitter failed to find a legal placement for all periphery components 

Info (14987): The following components had the most difficulty being legally placed: 

Info (175029): Clock core fanout containing node LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:1:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|gwt_tx_top:gwt_tx_4|tx_fifo:tx_fifo_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_k1t1:auto_generated|altsyncram_5k91:fifo_ram|ram_block9a0 and 31 other node(s) driven by auto-promoted clock driver  

... 

Info (175029): Clock core fanout containing node LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|gwt_rx_top:gwt_rx_5|pile_and_shift:PILE|data_scrambler_input[106] and 948 other node(s) driven by auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_rx_pld_pcs_interface_pld_pcs_rx_clk_out~CLKENA0 and auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:3:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (9%) 

Info (175029): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_rx_pld_pcs_interface_pld_pcs_rx_clk_out~CLKENA0 (6%) 

Info (175029): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out~CLKENA0 (5%) 

Error (14986): After placing as many components as possible, the following errors remain: 

Error (13081): The Fitter cannot route to 1 clock core fanout 

Info (14596): Information about the failing component(s): 

Info (13207): The clock core fanout consists of 40 node(s) 

Info (13205): Sample node name: LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|gwt_tx_top:gwt_tx_0|coe_GWT_TX[0] 

Info (13208): This core logic is driven by 1 clock source(s) 

Info (14900): auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out~CLKENA0 

Info (14894): This signal is currently using global clock 13, with the buffer placed at CLKCTRL_1C_G_I13 

Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (224, 213) due to related logic 

Info (175015): The I/O pad rx_gbt[24] is constrained to the location PIN_R3 due to: User Location Constraints (PIN_R3) 

Info (14709): The constrained I/O pad is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver 

Info (175015): The I/O pad rx_gbt[25] is constrained to the location PIN_P5 due to: User Location Constraints (PIN_P5) 

Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver 

Info (175015): The I/O pad rx_gbt[26] is constrained to the location PIN_N3 due to: User Location Constraints (PIN_N3) 

Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver 

Info (175015): The I/O pad rx_gbt[27] is constrained to the location PIN_M5 due to: User Location Constraints (PIN_M5) 

Info (14709): The constrained I/O pad is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_8G_RX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_10G_TX_PCS, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver 

... 

Error (16234): No legal location could be found out of 30 considered location(s). Reasons why each location could not be used are summarized below: 

Error (177032): Section clock (SCLK) network in spine clock region bounded by (111,87) and (159,113) is overused 

Info (18630): This congestion may be avoided by moving or disabling promotion of any of the following competing signals: 

Info (175030): Unroutable signal: 

Info (175026): Source: auto-promoted clock driver LLI:lli_inst|GWT_6ch:\multiLink_gen_loop:4:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out~CLKENA0 

Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (224, 213) due to related logic 

Info (175015): The I/O pad rx_gbt[24] is constrained to the location PIN_R3 due to: User Location Constraints (PIN_R3) 

Info (14709): The constrained I/O pad is contained within a HSSI_DUPLEX_CHANNEL_CLUSTER, which contains a HSSI_AVMM_IF, which drives a HSSI_TX_PLD_PCS_INTERFACE, which drives this auto-promoted clock driver 

...
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Altera_Forum
Honored Contributor I
106 Views

I managed to fix this by setting the clocks to non-global clock. Here's the constraint that did the trick. There must be one constraint like this per channel. 

 

set_instance_assignment -name GLOBAL_SIGNAL OFF -to "LLI:lli_inst|GWT_6ch:\\multiLink_gen_loop:1:multiLink_gen_gwt:u0|GWT_6ch_GWT_BANK_10_up7bqka:gwt_bank_0|GWT_6ch_altera_xcvr_native_a10_161_pn5wopi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|out_pld_pcs_rx_clk_out" 

 

Karol.