Arria II GX - Using 'external PLL' for ALTLVDS_RX

[Altera_Forum]

Hello everyone,

I am new to the world of FPGA's. and am currently using the Arria II GX FPGA along with Quartus II 10. 1 trying to implement the LVDS Receiver. I would like to use an 'external PLL' to clock the ALTLVDS_RX due to limited availability PLL resources in my design. 

The LVDS_RX, rx_in[],receives data from 13 channels at 250 MHz - which is to be serialized with a deserializartion factor of 10. 

I have enabled the 'external PLL' option on Page 1 of the MegaWizard Plug-in and I have an ALTPLL instantiated in my design. I went through some of the documentation from Altera regarding how to use the ALTLVDS, but I have some basic doubts . So - 

1. Would driving my ALTLVDS_RX rx_inclock with 250 MHz from the ALTPLL do the job?
2. The ALTLVDS_RX just has one output, rx_out[]. How can I synchronize with the output of the ALTLVDS_RX rx_out[]?
3. Do I also need to enable the DPA Alignment mode(?), as I noticed that I get a rx_sync_clock at the input of the ALT_LVDS_RX with this option enabled.

Would be great to get some information on this. 

Cheers!