Hello,
I have a Timing delay problem with the ARRIA V device.
I have a 100Mhz clock input in a CLK<#>N (not CLK<#>P) pin which has NO dedicated connections to the PLL. And I am using the PLL in NORMAL MODE " An internal clock in normal mode is phase-aligned to the input clock pin".
- In general (when clock input is CLK<#>P), Can you explain what exactly the PLL compensate for in NORMAL MODE???
Does it compensate for the delay from clock I/O input delay to PLL input OR does it compensate for the delay from the PLL output to the Registers input ??
OR both of them ??
- In my case, clock input is in CLK<#>N (not CLK<#>P) pin which has NO dedicated connections to the PLL. I used a Mega Wizard CLOCK CONTROL IP In order to rout CLK<#>N to PLL but this connection has a 9nsec .
What can I do to compensate this delay?
- I tried to change PLL phase shift in MEGAWIZARD but I still see the same delays in TIME QUEST. Can somebody explain this ??
Many thanks
