Arria10 FPGA transciever FEC specifications

[Romain_D]

Hello,

I am looking for specifications of the FEC used in the Arria10 FPGA transciever, more specifically its theoretical performance (maximum BER at input for error-free output, burst error size that would defeat error correction, etc.). All the information I could find is here: Intel® Arria® 10 Transceiver PHY User Guide, 2.6.2. It says the FEC 64b/66b but that is it. Where can I find more information on this?

Thank you,

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RD

[skbeh · Accepted solution]

Hi Romain

A10 transceiver Native PHY with FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10e12.

Refer section 2.9. Other Protocols

https://www.intel.com/content/www/us/en/docs/programmable/683617/

[Romain_D]

Hi @skbeh ,

Thank you for the intel. I found what I was looking for by following a resource mentioned mentioned in the document you linked:

"The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE 802.3ap-2007"
IEEE 802.3ap-2007 contained everything I was looking for.

Thank you,

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RD