Arria10 GX Unused Pin Handling

[Yamada1]

I was designing a design targeting 10AX027H3F35E2SG, but I couldn't fit the design We are planning to change to 10AX066K3F35E2SG.

Since the board has been manufactured, I would like to replace it, but it would be helpful if you could teach me about the following points.

1) All pins of BANK 2I (including power supply and GND) are unconnected. Will it affect the operation of other BANKs?

2) All pins (including power supply) of BANK 1D and 1E are unconnected. Will it affect the operation of other BANKs? I am using PLL.

I apologize for the inconvenience, but it would be helpful if you could teach me.

[FvM]

Refer to pin connection guideline, all GND pins need to be connected. IO banks may be powered down (except for 2A) if the related IO pins are not driven above 1.1 V. If I understand right, you can't fulfill the GND connection requirement. Correct FPGA operation is respectively not guaranteed, you may want to check if works though.

[lixy]

Hi Yamada, 

About the first question, what FvM said is correct. We can power down the VCCIO if the that I/O bank is unused. You can see this from the KDB below: https://www.intel.com/content/www/us/en/support/programmable/articles/000076285.html

You just need to pay attention that you should still connect these VCCIO pins to GND instead of floating. Also, there are always multiple VCCIO2I for 2I bank, make sure that all the VCCIO2I are connected to GND. 

However, if you power down the power supply only for Power Saving, power down this unused I/O would not make much difference. So we recommend user to connect the VCCIO even the bank is not used. 

About the second question, in Arria 10 Pin Connection Guideline, you can find that the PLL power supply is VCCA_PLL. VCCIO is basically for I/O buffer.

Anyway, we still recommend you to connect all the VCCIO even if the bank is not used.

Thanks & Regards,

Xiaoyan