Asynch Design Challenge

[Altera_Forum]

After all the chat in this thread (http://www.alteraforum.com/forum/showthread.php?t=26151)regarding glitching in the outputs of asynchronous logic, I thought I would post the following challenge for people to discuss: 

 Design a circuit to divide a clock by 3, keeping a 1:1 mark to space ratio and to start working instantly with no delay. i.e. using a PLL isn't allowed. I will allow a reset pulse to get things going in simulation in a known state but a real implementation shouldn't need it.  Extra bonus points for using the smallest amount of LEs.  http://farm5.static.flickr.com/4131/5144985871_0171bb6cc5_z.jpg   I'm rather proud of my solution which only uses three LEs (though it does have drawbacks). I'll post it in a couple of days so people can have a think about it first.

[Altera_Forum]

I can do it with two sync reset DFFs, a toggle FF and a 2 input AND gate which I think should fit in 3 LEs. 

The following pseudo code shows how I connect the above stuff.  reg r1, r2, clkout: always @ (posedge clkin) begin if (reset) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= 1'b0; end else if (r1 & r2) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= ~clkout; end else begin r1 <= 1'b1; r2 <= r1; end end

[Altera_Forum]

It's a serial topic in electronic forums (and in job interviews, too). You can e.g. search edaboard.com for "divide by 3".

[Altera_Forum]

I am afraid Cris72 that your code doesn't appear to work. I would also guess that the mark to space won't be that good either once corrected (though probably good enough for most people).

[Altera_Forum]

--- Quote Start ---  It's a serial topic in electronic forums (and in job interviews, too). You can e.g. search edaboard.com for "divide by 3".  --- Quote End ---   Ah, that must have been how I came across it the first time (it would have been a while ago :oops:)  Links: http://www.edaboard.com/thread48149.html http://www.edaboard.com/thread87765.html http://bbs.weeqoo.com/forum/download..._made_easy.pdf (http://bbs.weeqoo.com/forum/downloadfile.aspx?fu=uploadfile%2f2008%2f10%2f28%2f200810282151774.pdf&fillname=clock_dividers_made_easy.pdf)   It does appear to be a popular subject.  Interestingly, my solution differs from those seen so far as it doesn't use any latches at all.

[Altera_Forum]

--- Quote Start ---   am afraid Cris72 that your code doesn't appear to work.  --- Quote End ---   It's a representing a /6 rather than a /3 frequency divider.

[Altera_Forum]

--- Quote Start ---  It's a representing a /6 rather than a /3 frequency divider.  --- Quote End ---    FvM, you are right. I wrote the code by heart and I forgot that I must clock registers on both pos and neg clock edges. Here is the 'real' working code; this time I also tested it with ModelSim  module divider3 ( reset, clkin, clkout ); input reset; input clkin; output clkout; reg r1, r2, clkout; always @ (posedge clkin or negedge clkin) begin if (reset) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= 1'b0; end else if (r1 & r2) begin r1 <= 1'b0; r2 <= 1'b0; clkout <= ~clkout; end else begin r1 <= 1'b1; r2 <= r1; end end endmodule   To Bat: I think the code is working and the mark to space is good, both in the initial /6 version and in the correct /3. Why not? If I remember correctly I already used this type circuit many years ago and it worked perfectly, with 50/50 duty cycle and no glitches.  Regards Cris

[Altera_Forum]

Cris72, are you compiling that in ModelSim or Quartus 2? Within Quartus 2 I'm getting the following: 

 Error (10239): Verilog HDL Always Construct error at asynchclockdiv.v(21): event control cannot test for both positive and negative edges of variable "clkin"  line 21 is "always @ (posedge clkin or negedge clkin)"  If you can trigger off both edges of the clock then the design of a div 3 is trivial. However, this isn't something you can easily do in Altera FPGAs. (at least that is my understanding).  You are right though about the mark to space, I wasn't looking carefully enough at how your code worked.

[Altera_Forum]

I'm always up for fun. It so happens I've never done this one before. How about this. It results in 2 ALUTs and 2 Registers. 

 module div_by_3( input clkin, output reg clkout ); wire rstn; reg clkout_r; wire clkout_r_n; assign clkout_r_n = ~clkout_r; assign rstn = clkout_r_n | clkin; always @(posedge clkin or negedge rstn) if(~rstn) clkout <= 1'b0; else clkout <= clkout_r_n; always @(posedge clkin) clkout_r <= clkout; initial begin clkout = 1'b0; clkout_r = 1'b0; end endmodule   Here's a shot from the RTL viewer:

[Altera_Forum]

It looks good. 2 LEs (according to Quartus way of counting resources) can't be beaten.

[Altera_Forum]

2 LEs is good. I didn't think that would have been possible but you have proven me wrong. I'd post my design but I've a PC power supply failure to work around at the moment which is a pain. 

 Try coming up with a latch free design (ok one that doesn't use the LE latch - I guess my solution could be considered to have a form of latch in it though made from combinatorial logic)

[Altera_Forum]

For clarity, we should distinguish between synchronous register (or FF) and asynchronous latch (which is implemented by Quartus mostly as logic loop).

[Altera_Forum]

Ok, I've received my new power supply so I'm up and running again. 

 This is my latchless design which requires three LUTs:  module asynchclockdiv ( input wire clkin, input wire reset, output wire clkout ); wire q2, q1, q0 /* synthesis keep */; assign q0 = ((clkin & !q2) | (clkin & q0) | (!q2 & q0)) & !reset; assign q1 = ((!clkin & q1) | (!clkin & q0) | (q1 &q0)) & !reset; assign q2 = (!clkin & q2 & q0) | (clkin & q2 & !q0) | (clkin & q1 & q0) | (q2 & q1); assign clkout = q2; endmodule It operates as a 6 state machine with the other two states transforming into the normal modes so it should always power up and start working.  It isn't a design I would recommend for anything other than an exercise as it is very easy to break. For example, if q2 was gated with the reset line like q0 and q1 then it no longer fits into a single LE, glitching occurs and the result isn't correct.  jakobjones solution makes me think it may be possible to do an async design with two LEs also. I will have to have a think about that.