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FPGA synthesis never implements any resource that isn't "actually used". I guess the problem is that you don't understand which part of the code infers a RAM based shift register. But without seeing the code, it's hard to tell.
The hierarchy view already tells you that it's used in the implementation of dataodd_rtl. There's no additional autogenerated logic, it's just the way how altshift_taps is implemented.
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I used data odd here :
BEGIN
IF (rising_edge (clk)) THEN
Splitter<=Original(generaladdress);
dataeven <= Splitter(9 downto 0);
dataodd<=Splitter(19 downto 10);
if kk=2 then
First_Reg<=dataeven;
else
evenbuff<= dataeven;
end if;
xoddbuff<=dataodd;
oddbuff<=xoddbuff;
It temporary holding a value since I need to wait for one clock cycle, however, I defined it as signal of unsigned, I don't know why it used as m4k?
