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So my NIOS code has outgrown the available on chip RAM and I've moved it to off chip SDRAM. Very slow, but I fire up Eclipse and I can get it to run. I need to get it to run automatically and I've found snippets of information by perusing the NIOSII software developers Handbook but can anyone point me to definitive documentation. I know I need to persuade the compiler to produce a ROM image that becomes a MIF, which I believe it does, and get something (maybe a bootloader) to do the initialisation, and somewhere I need to tell the tools to run that code.
Can anyone help with the blanks?
Link Copied
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Hi,
Please follow the example from scratch in Embedded Design Handbook.
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I've followed the links and looked for an example project but can't find one. I don't know that I have the exact hardware to test it on. Besides, what would it prove if the example works? All I'm really asking for is a fault finding flow chart so I can narrow down which step is wrong.
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Hi,
From the doc, there is a image on the "Hardware Design" shows the Platform Designer and the connections made of each IP. You can handpicked the IPs shown and connect them accordingly, which will get you the hardware design example.
Then follow the steps for the "Nios® II Processor Application Copied from EPCQ Flash to RAM Using Boot Copier" section.
I guess the first issue is to get the epcq controller to be your reset vector.
Then, back to your original issue, to try this example and build it up until the .jic programming file and program it to your board and tests.
With the .jic you can do a reset on your FPGA device using the reset button or power cycle.
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Just to re-iterate, I got the EPQC reset option sorted when I used the Flash controller V2. Same symptoms though, the FPGA configures but the NIOS2 doesn't run and now I can't connect with the debugger. Going round the loop described in the handbook a dozen times and getting the same results isn't helping me debug my problem.
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Hi,
The previous design you shared, you were able to run from debugger correct?
So for the new one, you were not able to?
If Quartus compilation have no issues, then the only thing I would check would be the Application & Programming part, on getting the .hex from Nios II eclipse without error.
Then generating the proper programming files and program it successfully.
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@EBERLAZARE_I_Intel wrote:If Quartus compilation have no issues, then the only thing I would check would be the Application & Programming part, on getting the .hex from Nios II eclipse without error.
What can I check and how? This is the crux of my problem
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Hi,
Any errors during your Nios II build when generating the .hex steps?
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Hi,
Which file are your programming into your board, is it the .jic file?
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Hi,
If there are no error from Quartus/Nios II SBT, you might need to check your configuration in your Quartus design and you MSEL pin of your board.
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Everything, I repeat everything, works except the booting with code in external memory. The FPGA configures, the custom logic works, the NIOS2 runs my code if I debug from Eclipse without trying to boot from external memory. How do I debug why it wont boot? The handbook just gives me a great long sequence of instructions with no guidance on figuring out which step I've done wrong.
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Hi,
I am will provide you the example for Quartus 20.1 Lite based on the doc, allow me a few days to get this to you.
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Hi,
I send the design to your email.
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Hi,
I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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As per email discussion, this problem is still unresolved and has moved up in priority.

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