Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20688 Discussions

Avalon SPI Interface: Bus width?

Altera_Forum
Honored Contributor II
‎09-18-2015 01:11 PM
954 Views

when using the SPI avalon interface function "alt_avalon_spi_command", it supports only 8bit bus width. Is there another way (function) to send also 16bit? 

 

Thanks!
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-22-2015 02:54 PM
216 Views

Hi Hugo, 

 

You could write your own version of the spi_read / spi_write functions using IORD and IOWR directly. The Embedded Peripherals IP User Guide is a good reference on how to do that manually 

 

Cheers, 

Thiago
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.