Avalon Slave Uart Problem

[Altera_Forum]

I have a Phycore 5200B I/O Board having MPC 5200 core and a Cyclon 2 FPGA on it. 

In my system MPC5200 is used as a core and an avalon uart is implemented in the Cyclopn 2 FPGA.   I am using the MPC 5200's local plus bus to communicate with the FPGA and a lpb_to_avalon interface is of course used for conversion of signal levels from local plus bus to avalon bus.   I generate a system in SOPC using an avalon uart as an avalon slave and the interface component (lpb_to_avalon) as an avalon master.I made base address of the uart as 0x00000000 ending @ 0x0000001f in SOPC.   I have placed FPGA in core's address space (in main.cpp) as  #define fpga 0xe2000000 In the nios uart datasheet,it shows the internal registers of the uart as having corresponding addresses with offset 1 from base address of the uart.For example the txdata register is @ offset 1 and registers are all 16 bits long.   **offset** **register**  0 RO rxdata (16 bits long,15..8 are reserved,7..0 are rxdata) 1 WO txdata (16 bits long,15..8 are reserved,7..0 are txdata) 2 RW status .... 3 RW control .... .  . 5 .. endofpacket (The avalon slave uart has address inputs as A2 A1 A0 (3 bits),so offset is upto 5) **I have attached that nios uart datasheet also !   In normal operation, from the datasheet,if I am to write data to txdata,I should use the convention *(uint16*)(fpga+2)=0xa5; (in main.cpp) as there are 16 bits in each register in the uart i offset the FPGA base address by 2=16bits and start writing from txdata register shown in datasheet,but this is not the case in avalon uart's point of view,unfortunately:  As I write some bits into UART's txdata register from MPC5200 side (in a main.cpp file) , it is interesting that the data is sent to uart's tx_out pin if I write it either as *(uint32*) (fpga+1)=0xa5 or as *(uint32*)(fpga+2) =0xa5,so the second write operation should write to status register as in datasheet but it is seen in the txout pin of the uart in FPGA.   Also,if I use *(uint16*)(fpga+1)=0xa5,I see nothing transmitted.(Also if I open the exceptions for a timer,sometimes I get alignment exception in  *(uint32*)(fpga+1) convention)   I wonder if there is a problem with the uart's internal registers' places differing from the datasheet or is there any other serious problem with address alignment.   I have used 2 pio implemented in the FPGA in sopc to test the addressing of the MPC5200's local plus bus to avalon bus,and made the pio1 as base address starting @ 0x00000000 and ending @ 0x0000000f in sopc,other one pio2 as starting @ 0x00000010 and endin @0x0000001f.   Then, I generated the system and programmed the FPGA. Then, in the same main.cpp,I writed to pio1 as *(uint32*)(fpga)=0x01 and it worked,also I tried *(uint16*)(fpga)=0x01 and it worked again. Then, I tried to write the second pio2 as *(uint32*)(fpga+10 )=0x01 and it did'nt work.Then, I wrote it as *(uint32*)(fpga+0x10)=0x01 and it worked. Also 16 bit and 32 bit casting did not make difference in pio examples,but the 16 bit casting didnot work in uart example.   This is part of one very important project and i am pleased if anyone can make a suggestion. Thanx in advance..

[Altera_Forum]

The problem is, 

In the datasheet of the nios uart,it is said that if you use HAL provided by the altera,you can not directly access UART's internal registers,the registers are for only users who are writing drivers for the core,so how can i access the UART's intrernal registers from the MPC5200 core?